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Setting exact ADC sample rate in the Concerto device

Alexey Tsirlin
Intellectual 555 points

I am considering to migrate one of our projects to Concerto family and I am trying to better understand the ADC subsystem of the device.

My application requires constant sample rate ADC with long ping-pong buffering (few hundreds of samples each buffer). The required sample rate is 2.4MSps and I am planning on running the system with 144MHz, which dictates the ADC clock of 36MHz. Each conversion should be done in 15 ADC clocks (36/2.4 = 15) which is less than the minimal number of clocks for the single conversion (13+7 = 20). So some amount of pipe-lining is required here (and as I understand it is possible as the minimal number of cycles for single conversion is 13 according to data-sheet - 37.5/2.888 = 13). I cannot really understand from the user manual of Concerto family, how is the pipe-lining of the conversions is achieved for single ADC input. Can you please point me in the correct direction?

Thanks,

Alexey.

  • 0
    TI__Guru 60865 points

    The short answer is that (in overlap mode) there are always 7 cycles of overlap and always 13 cycles of conversion time.  For the minimum acquisition window width of 7 cycles, this gives you an effective sample rate of:

    effective cycles per sample = 7 (acquisition window) + 13 (conversion time) - 7(overlapped cycles) = 13 cycles

    For an acquisition window width of 9 cycles:

    effective cycles per sample = 9 (acquisition window) + 13 (conversion time) - 7 (overlapped cycles) = 15 cycles

    The things that are actually overlapped are the first 7 cycles of the acquisition window (of the nth conversion) with the last 7 cycles of the voltage conversion (of the n-1 th conversion). 

    You can get this and additional information starting around figure 11-40 in the TRM, although it is unfortuntely not completely clear what happens with increased acquisition window without some thourough reading of the rest of the documentation. 

  • 0 in reply to Devin Cottier
    Intellectual 555 points

    Hi,

    I think I understand the overlap function now. BTW, is it related to ADCNONOVERLAP bit in ADCCTL2 register? I cannot find anything about this bit in user manual other than few lines in the registers description section.

     

    Thanks,

    Alexey.

  • 0 in reply to Alexey Tsirlin
    TI__Guru 60865 points

    Setting that bit disables the overlap in the ADC converter (so you can no longer subtract out the 7 cycles ).  It is not set by default and I think you are going to want to leave it that way.  This bit goes back to the Piccolo series ADCs (which are similar to the Concerto ADCs); it was used as a workaround for an issue with the first sample.