This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Error -1135 @ 0x0 when debugging F28335

Other Parts Discussed in Thread: TPD8F003, CONTROLSUITE, TPS3828

I posted previously in the thread F28335 Unable to Program and XRS Periodically Asserting Low.  I'm having problems still though.

Our 1st custom board in the above thread was still having some issues with power, to the point that the success in programming started dropping to 0%.  I also noticed that the chip didn't appear to run on its own without the debugger, though I was going to try moving the watchdog disable a bit closer to the start to see if that was the issue.  I was never able to reprogram it though.

So we made a fresh copy of our custom board with all the fixes from our trial with board #1.  I powered it up and connected the XDS100v3 to it from CCS v5.4.  I ran the "Test Connection" in the ccxml file and the JTAG scan paths for DR and IR succeeded with no errors.

But, when I entered debug, I get the error:

C28xx: Error connecting to the target: (Error -1135 @ 0x0) The emulator reported an error. Confirm emulator configuration and connections, reset the emulator, and retry the operation. (Emulation package 5.1.73.0)

I've noticed in other threads this is often accompanied by another error, but this is the one I get every single time.  I've run the "Test Connection" a few more times at different rates (10 kHz, 100 kHz, 1 MHz) and they always check out but I still get Error -1135.

I have the JTAG wired generally as specified in the F28335 manual:

The difference is I have a compact TI 20-pin on the XDS100v3, so in addition I also have:

15 SRST - connected to input MR' pin of the power supervisor TPS3828-33, whose output RESET' goes to the F28335 pin XRS'
16 ground
17 no connection
18 No connection
19 no connection
20 ground

In the path between the JTAG port and the F28335, I also have Littelfuse LC03-3.3 transient protectors (EFT and surge rated) and the EMI filter TPD8F003DQDR.  I've used the TPD8F003 successfully in JTAG on a Stellaris project before, but the LC03-3.3 is new to this design, I might try removing them next.

Any ideas what the issue is?

For reference, here is my JTAG scan test results:

[Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\DOCUME~1\USER\LOCALS~1\APPLIC~1\.TI\1989394224\
    0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusbv3.dll'.
The library build date was 'Apr  1 2013'.
The library build time was '23:55:08'.
The library package version is '5.1.73.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

  Test  Size   Coord      MHz    Flag  Result       Description
  ~~~~  ~~~~  ~~~~~~~  ~~~~~~~~  ~~~~  ~~~~~~~~~~~  ~~~~~~~~~~~~~~~~~~~
    1    512  - 01 00  500.0kHz   O    good value   measure path length
    2    512  + 00 00  1.000MHz  [O]   good value   apply explicit tclk

There is no hardware for measuring the JTAG TCLK frequency.

In the scan-path tests:
The test length was 16384 bits.
The JTAG IR length was 3 bits.
The JTAG DR length was 1 bits.

The IR/DR scan-path tests used 2 frequencies.
The IR/DR scan-path tests used 500.0kHz as the initial frequency.
The IR/DR scan-path tests used 1.000MHz as the highest frequency.
The IR/DR scan-path tests used 1.000MHz as the final frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 512 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 3 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End]

  • I removed all of the Littelfuse LC03-3.3 so the only thing between the JTAG port and the F28335 is the TPD8F003, which worked fine on my Stellaris project.

    I'm still getting the same error:

    Error connecting to the target:
    (Error -1135 @ 0x0)
    The emulator reported an error. Confirm emulator configuration and connections, reset the emulator, and retry the operation.
    (Emulation package 5.1.73.0)

  • Andrew,

    It looks like the JTAG portion is correct.  The only oddity I see is:  The emulator connectivity screenshot you've attached shows VDDIO, is this signal 3.3V in your system?  In its most recent reincarnation have you ever been able to connect to the MCU?

    I lean toward this being some problem in the 'life-support' circuitry surrounding the F28335. 

    -Make sure the crystal outputs properly to the F28335 (usually is about 20MHz in our systems)
    -Make sure that the power supply is stable
    -May be worthwhile to try to change the boot mode to 'SCI boot mode' or something non-FLASH. 

    The schematics for the F28335 controlCARD may be something that you can compare your design to.  (note that it is overdesigned in some places such as the LC power filtering)
    \controlSUITE\development_kits\~controlCARDs\CC2833xHWdevPkg\F28335controlCARD HWDevPkg ZJZ [R2.2]\

    Hopefully this helps.


    Thank you,
    Brett

  • Yes, VDDIO is +3.3 V in our system.  It's the same for the pull-ups in the JTAG connection at the top right of the schematic for the F28335 controlCARD.  Though I used F28335controlCARD HWDevPkg PGF [R1.0] as a reference as we're not using the BGA version.

    I have checked the +5 voltage supplying the regulators of +3.3 V and +1.9 V for the F28335.  All three voltages look stable on the oscilloscope.

    We have chosen a 32 MHz crystal (the controlCARD uses a 30 MHz) and I see a sine wave output of 32 MHz on both pins of the crystal.  X2 has an amplitude from a little under 0 V and a little over +2 V, X1 has an amplitude as low as a little over 0V to a little below +2 V.

    I'm double checking the voltage and ground connections again, but they checked out on the first board (I did continuity checks between the power pins to either +1.9 V or +3.3 V with the power off, and same for grounds).  We have decoupling capacitors similar to the controlCARD, 100 nF in about the same distribution though we don't have the inductors for the pi filter on the power pins like the controlCARD.

    I'll keep checking here and recheck if there's any other differences with the controlCARD schematic.

  • One extra question, is XRSn pulsing every so often as in your previous design?  If so, how often?  Is it a square wave?


    -Brett

  • Yes, it is doing it, and it is a square wave.  Here is a drawing of it.  The scope I have at the moment doesn't have a USB port, but I could get an actual trace of any signals.

    I checked out continuity on all +3.3 V, +1.9 V, and ground connections on the chip and they all seem ok still. I did see one difference, our XRS' pin does not have an external 2k Ohm pull-up to +3.3 V or a 100 nF capacitor to ground like the controlCARD.  The power supervisor TPS3828 is in place though.

    I could maybe upload the relevant portion of our schematic?

    I will try changing the boot mode but that will mean cutting some short traces; that might have to wait until the morning.

  • Though the XRS' line does stay high during and after the JTAG connection test and when I attempt to load a program.

  • Hi Brett,

    I grounded GPIO84/XA12 pin 169 to put it in SCI-A boot mode.  I noticed that the XRS' pin (XRSn) wasn't pulsing anymore on power-up without the JTAG connected.  XRS' stays high at +3.3 V continuously.

    The JTAG test still passes but I still get the same error when trying to load the program:

    Error connecting to the target:
    (Error -1135 @ 0x0)
    The emulator reported an error. Confirm emulator configuration and connections, reset the emulator, and retry the operation.
    (Emulation package 5.1.73.0)

    I've gotten this error about 50 times now, and I failed to answer your earlier question, I have never been able to program the chip on this new board.  One time when retrying, I did get a different error, but only once out of 50 or so trials:

    C28xx: Error connecting to the target: (Error -182 @ 0x0) The controller has detected a cable break that is near-to itself. The user must connect the cable/pod to the controller. (Emulation package 5.1.73.0)

    To put actual numbers on the power stability:

    +3.3 V:  Majority of ripple contained in +/- 12 mV envelope, with damped sinusoidal transients every 8.4 ms that have a decreasing exponential of duration 12 us with an initial peak amplitude of 60 mV.

    Uses a AP7333 regulator with +5 V input.  300 mA max.

    +1.9 V: Same ripple and transient structure as +3.3V.

    Uses a NX1117CE19Z regulator with +5 V input.   1 A max.

    What should we check or try next?

  • Andrew,

    Some thoughts:
    1) From above I believe you are using the xds100v3 emulator, correct? 
    2) Do you happen to have another emulator available that you can quickly try?
    3) You can upload a file to the forum if you're comfortable with that.  Or you could upload a partial schematic.  Or you could friend me and we can handle it there.


    Thank you,
    Brett

  • Yes, it's the Spectrum Digital XDS100v3; we only have two of those as far as emulators go.

    I think we'll try swapping out the F28335 for a new one tomorrow.  I'll try to get the schematic to you some way.

  • We replaced the F28335 for a new one and that was the problem.  Apparently it was bad part, heat, or static damage; the board was fine.