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F2806x SPI, SCI max baud rate

StephanS
Genius 4036 points

Hi,

I am a little bit in doubt about the max baud rate for the 2806x SPI and SCI:

When having a system clock of 90MHz and also LSPCLK at 90MHz, I could get

SCI: max.Baudrate=LSPCLK/16 (BRR=0 or 1) = 5.625 MHz

SPI: max.Baudrate=LSPCLK/4 (SPIBRR=0..3) = 22.5 MHz

In the datasheets sprs698d and spruh18d, I found no limits for SCI, so the 5,625 MHz seems to be okay !?

I found limits for the SP:

Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.

The general GPIO limits are given as max. 20MHz toggling frequency.

So what is the SPI limit? Can it be operated with a 90MHz LSPCLK? Does the baudrate have to be at <= 10MHz (SPIBRR=8) ?

I think, the datasheet is not really clear about this.

For McBSP in SPI mode, I found "With maximum LSPCLK speed of 90 MHz, CLKX maximum frequency is LSPCLK/16 , that is 5.625 MHz".

Any help is appreciated.

  • 0
    TI__Guru 61235 points

    Stephan,

    Peripheral pin toggling is limited by the 20 MHz rate of the pin buffers.  So regardless of other calculations, you cannot go faster than that on a serial port.  SCI is OK at the 5.625 MHz as you showed, although that is fast for an asynchronous communication so you need to have very good clock rate agreement between the transmitter and receiver to get it to work.

    For SPI, slave mode is slower to begin with because the slave does not generate the clock.  Therefore, it has to react to the incoming clock and this slows the maximum baud rate down.  In master mode, the reason master receiver is half that of master transmitter is because of round-trip signal skew.  The clock has to travel from the master to the slave.  The slave then sends the data out.  The data travels back to the master where it is received.  By the time this round-trip process is completed, there can be considerable skew between the edges on the data the slave sends and the clock being generated by the master.  The master latches the incoming data based on the clock is is sending out, which doesn't have any round-trip skew.  The specs in the datasheet reflect the practical limits that TI has observed for typical system setups.

    The McBSP is a different serial port than SPI, and in SPI mode the McBSP has different speed limits.  If the documentation shows LSPCLK/16, then that's the limit.

    Regards,

    David

  • 0 in reply to David M. Alter
    Genius 4036 points

    David,

    thanks for the answer.

    So I will stay at 5.625 MHz (SCI, only theoretical, and McBSP) and 10 MHz for SPI when transmitting and receiving (SPIBRR=8 at LSPCLK=90 MHz).

    Stephan