failure on Xintf initialization

Zachary,

On F2812 device, the XINTF is active by default out of reset.  Timings are all configured for maximum (meaning, slowest) since this is safe.  You should be able to link your .ebss section to external memory without issue.  During your C software intialization, you should configure the XINTF timings to speed things up, as allowed by your external memory timings.  I've attached an example of a XINTF initialization routine in C.  You need to check the timing for your memory and adjust the code as needed.

The only weakness of doing the XINTF setup during program initialization is that the .cinit to .ebss/.bss copy (done by _c_int00, before main) will be slow because the XINTF timings are still at maximum.  But then the flash wait-states are also at maximum during this time so everything is running slowly.  In applications that require a faster bootup, the user needs to run some assembly code prior to _c_int00 to get the flash and XINTF timings configured.

F28335 is different because the GPIO pins are not configured for XINTF function after reset.  Therefore, the user has to do some special stuff to get things running before the C environment can be setup by the code.

Regards,

David

David,

Thanks for your reply , I tried to link my .ebss section to external memory without any initialization before opening this post , and it turns out it failed out with warning " data verification failed at address please verify target memory and memory map" after uploading the program. I have read some post which claim that an initialization is required before using external memory.  I tried to use official  Xintf.c to initialize as well, which didnt work out for me , hence , I opened this post seeking helping.

The official  Xintf.c :

XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
// No write buffering
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE = 1;

// Zone 0------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING0.bit.XWRLEAD = 3;
XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING0.bit.XRDLEAD = 3;
XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
XintfRegs.XTIMING0.bit.XRDTRAIL = 3;

// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING0.bit.X2TIMING = 1;

// Zone will sample XREADY signal
XintfRegs.XTIMING0.bit.USEREADY = 1;
XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous

// Size must be 1,1 - other values are reserved
XintfRegs.XTIMING0.bit.XSIZE = 3;

// Zone 1------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING1.bit.XWRLEAD = 3;
XintfRegs.XTIMING1.bit.XWRACTIVE = 7;
XintfRegs.XTIMING1.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING1.bit.XRDLEAD = 3;
XintfRegs.XTIMING1.bit.XRDACTIVE = 7;
XintfRegs.XTIMING1.bit.XRDTRAIL = 3;

// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING1.bit.X2TIMING = 1;

// Zone will sample XREADY signal
XintfRegs.XTIMING1.bit.USEREADY = 1;
XintfRegs.XTIMING1.bit.READYMODE = 1; // sample asynchronous

// Size must be 1,1 - other values are reserved
XintfRegs.XTIMING1.bit.XSIZE = 3;

// Zone 2------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING2.bit.XWRLEAD = 3;
XintfRegs.XTIMING2.bit.XWRACTIVE = 7;
XintfRegs.XTIMING2.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING2.bit.XRDLEAD = 3;
XintfRegs.XTIMING2.bit.XRDACTIVE = 7;
XintfRegs.XTIMING2.bit.XRDTRAIL = 3;

// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING2.bit.X2TIMING = 1;

// Zone will sample XREADY signal
XintfRegs.XTIMING2.bit.USEREADY = 1;
XintfRegs.XTIMING2.bit.READYMODE = 1; // sample asynchronous

// Size must be 1,1 - other values are reserved
XintfRegs.XTIMING2.bit.XSIZE = 3;

// Zone 6------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING6.bit.XWRLEAD = 3;
XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING6.bit.XRDLEAD = 3;
XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
XintfRegs.XTIMING6.bit.XRDTRAIL = 3;

// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.X2TIMING = 1;

// Zone will sample XREADY signal
XintfRegs.XTIMING6.bit.USEREADY = 1;
XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous

// Size must be 1,1 - other values are reserved
XintfRegs.XTIMING6.bit.XSIZE = 3;

// Zone 7------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING7.bit.XWRLEAD = 3;
XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 3;
XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
XintfRegs.XTIMING7.bit.XRDTRAIL = 3;

// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.X2TIMING = 1;

// Zone will sample XREADY signal
XintfRegs.XTIMING7.bit.USEREADY = 1;
XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous

// Size must be 1,1 - other values are reserved
XintfRegs.XTIMING7.bit.XSIZE = 3;

// Bank switching
// Assume Zone 7 is slow, so add additional BCYC cycles
// when ever switching from Zone 7 to another Zone.
// This will help avoid bus contention.
XintfRegs.XBANK.bit.BANK = 7;
XintfRegs.XBANK.bit.BCYC = 7;

//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.

asm(" RPT #7 || NOP");

I am currently trying yours and I hope it works , thanks again for your help 

Regards,

Zachary

David,

It is still not working with your example of a XINTF, as i mentioned that I am still not even able to upload the program successfully, the upload progress ceased with following warning :

C28xx: File Loader: Data verification failed at address 0x00002000 Please verify target memory and memory map.
Error found during data verification.
Ensure the linker command file matches the memory map.

I am looking forward to your kindly helping again.

Regards,

Zachary

Zachary,

Zachary Wong said:

C28xx: File Loader: Data verification failed at address 0x00002000 Please verify target memory and memory map.
Error found during data verification.
Ensure the linker command file matches the memory map.

Address 0x00002000 is on external zone 0.  Your original post mentioned zone 6.  Do you have RAM connected to zone 0?

- David

David,

I tried your external memory interface testing code, it works fine, but I am still unable to upload the program which links the .ebss section to external memory interface. Every time I tried to upload the program , the data verification  warning occurred.  As I checked  ti wiki about data verification error, its pointed out that the most reason that makes this warning occur is not an issue of the memory range not existing at all, but that the memory has not yet been initialized.  That was why i though the problem might due to initialization instead.

http://processors.wiki.ti.com/index.php/Troubleshooting_CCS_-_Data_Verification_Errors#Available_Target_Memory

I have never doubted your professional, as I am not an english native speaker, so I may have offended you , even thought I didnt mean to, I sincerely apologize for any offense I may have made.

Thanks once again for you help,

Zachary

David,

That confuses me as well, since none is linked to external zone 0...

Regards,

Zachary

I have found out that there actually some code link to  zone0 which I forgot..

#define OutReg (*((volatile Uint16 *)0x20FF))
#define LedReg (*((volatile Uint16 *)0x21FF))
#define SysReg (*((volatile Uint16 *)0x22FF))
#define SDReg (*((volatile Uint16 *)0x23FF))
#define KeyReg (*((volatile Uint16 *)0x24FF))
#define InlReg (*((volatile Uint16 *)0x25FF))
#define UsbIntReg (*((volatile Uint16 *)0x26FF))
#define IntReg (*((volatile Uint16 *)0x27FF))

I think that may the problem causing the error , I am currently checking why the above-mentioned code section cause the probelm..

After some investigation, there is nothing deal with those above codes,

and I am trying to comment the Zone0 and Zone 1 :

// ZONE0 : origin = 0x002000, length = 0x002000 /* XINTF zone 0 */
// ZONE1 : origin = 0x004000, length = 0x002000 /* XINTF zone 1 */

After removing them in cmd file, I can now upload the program to f2812 sucessfully , but when I tried to run the program,

it went to "interrupt void ILLEGAL_ISR(void) "  , which is Illegal operation TRAP... I am current;y reading some post about Illegal operation TRAP

Hi Zachary,

You had mentioned concern in your previous post that I sounded offended.  Nothing of the sort.  You have been very polite and are making good use of the forums by posting necessary information so we can help you with your issue.  Perhaps my answer was short and gave you the impression I was offended.  We sometimes don't have time to write long responses here at TI.  But I thank you for your concern.

You've got something wrong someplace in your code.  Attach your linker .map file to this thread and I will take a look at it.  Maybe I'll spot something.

Regards,

David

David,

After some checking, I have found that the problem may not be concerned with the .map file, as I am now able to upload other programs to the f2812 with same .map even linking the .ebss to XINTF, I think maybe some of my codes go wrong , as the program was ram based , I am still checking where it goes wrong, but I really thank you for helping, as you lead me to correct direction , which I thought gel file and initialization of XINTF were the problems. at first If you read this post again, would you mind give me some suggestions or hints upon it? 

Regards,

Zachary

My current state is that I am able to upload other programs to f2812 , but when I tried to upload the program i have been wanted to upload, the data verification warning occurred still. If I remove the zone0 and zone1 in map file,  and upload it again, it can be uploaded successfully, but when I run the program , It goes to Illegal operation TRAP.. 

CMD:

MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

ZONE0 : origin = 0x002000, length = 0x002000 /* XINTF zone 0 */
 ZONE1 : origin = 0x004000, length = 0x002000 /* XINTF zone 1 */
RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
ZONE2 : origin = 0x080000, length = 0x080000 /* XINTF zone 2 */
ZONE6 : origin = 0x100000, length = 0x080000 /* XINTF zone 6 */
OTP : origin = 0x3D7800, length = 0x000800 /* on-chip OTP */
FLASHJ : origin = 0x3D8000, length = 0x008000 /* on-chip FLASH */
// FLASHI : origin = 0x3DA000, length = 0x002000 /* on-chip FLASH */
// FLASHH : origin = 0x3DC000, length = 0x004000 /* on-chip FLASH */
FLASHG : origin = 0x3E0000, length = 0x004000 /* on-chip FLASH */
FLASHF : origin = 0x3E4000, length = 0x004000 /* on-chip FLASH */
FLASHE : origin = 0x3E8000, length = 0x004000 /* on-chip FLASH */
FLASHD : origin = 0x3EC000, length = 0x004000 /* on-chip FLASH */
FLASHC : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x3F6000, length = 0x001F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */

/* ZONE7 : origin = 0x3FC000, length = 0x003FC0 /* XINTF zone 7 available if MP/MCn=1 */
ROM : origin = 0x3FF000, length = 0x000FC0 /* Boot ROM available if MP/MCn=0 */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM (MP/MCn=0) or XINTF zone 7 (MP/MCn=1) */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM (MP/MCn=0) or XINTF zone 7 (MP/MCn=1) */

PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */

RAMM0 : origin = 0x000000, length = 0x000400 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
FLASHB : origin = 0x3F4000, length = 0x002000 /* on-chip FLASH */
RAMH0 : origin = 0x3F8000, length = 0x002000 /* on-chip RAM block H0 */
}

/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/

SECTIONS
{

/* Allocate program areas: */
.cinit : > FLASHA PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : >FLASHJ PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = ZONE6,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0

csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0

/* Allocate uninitalized data sections: */
.stack : > RAMM0 PAGE = 1
.ebss : > ZONE6 PAGE = 0
.esysmem : > RAML1 PAGE = 1

/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0

/* Allocate IQ math areas: */
IQmath : > FLASHC PAGE = 0 /* Math Code */
IQmathTables : > ROM PAGE = 0, TYPE = NOLOAD /* Math Tables In ROM */

/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT

}

GEL:

GEL_MapAdd(0x2000,0,0x2000,1,1); /* XINTF ZONE 0 */
GEL_MapAdd(0x4000,0,0x2000,1,1); /* XINTF ZONE 1 */

Zachary,

I think you have some sort of linking issue (I know you think the same).

Does the code work when you don't try to use external memory?

Do you get any warnings when you build the project?  In particular, warnings about linking a section without any specification?

Attached the .map file from your project to this thread.  You don't have to paste the contents into a post.  When you make a post, click the 'Options' link at the top of the post and then you can attach the file directly.

- David

David,

That issue has been troubling me for like a week already :(

I cant try to not use external memory as the .ebss size is too large to fit into internal memory ...

All i got for the linking issue when building the program was about "creating output section "reset_vec" without a SECTIONS specification" I am sure if its related though..

Thanks for the hints anyways, 

Zachary