C28x Interrupt flag armada

Hello,

I have some question about the interrupt handling of the c28x based microcontrollers.

I tried to understand the interrupt handling of the Control Subsystem of a Concerto series microcontrollers however I can't see the whole picture on the system integration level: Core + Interrupt controller + Peripheries.

As I see right know there are 3 interrupt flags: Periphery flag (e.g. SPI INT flag) + PIE flag + CPU flag.

My questions are:

• Which of these I have to manually clear and which is cleared automatically by the core?
• As I see usually there is one interrupt flag in the periphery and the cause of the interrupt can be determined from status registers. Is this interpretation right?
• There is an issue about manual clear of the interrupt flag (for example you don't want to service the interrupt) in the PIE which is why the reference manual suggest that to configure a dummy (empty) routine which will clear this flag. The cause of this according to the ref. manual is you can loose incoming interrupts because: you read the value of the PIEIFR you mask it and you write it back and if the interrupt occurs between the read and write you are in problem. Here comes which I don't understand if there is flag in the periphery then it will be set until it is cleared so the interrupt request will be noticed in the next clock cycle. Could you explain what I understand wrong here? (edge sensitive circuitry or i don't know)