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Concerto Startup Problem

we have develop our own board for concerto F28M32H52C1.

I have written code for both C28 and M35 all modules and that is working fine with NEW board.

But day before when I was interfacing with SSI of M35 and FRAM, my program stop working.

Even my previous backup software program are not working in the same board. I tried with other board and the problem is same. New and Old program are not working.

Please help me if any one faced problem something like this.

 

  • Hi,

    I would like to know, what do you mean by "Not working/ Stop working" ?

    Are there any errors ? or Are you not able to debug ? or any other issue?

    Regards,

    Gautam

  • Hi,

    By debugging, I came to know that it goes into fault ISR.

    INVSTAT bit of FAULTSTAT Register is SET.

    How to find that where it is finding invalid state of instructions??

  • Hi,

    Ok, so did you check with all your ISRs? Remove unwanted interrupt based codes. First try by removing all the ISRs and debug. If successful (which should be), carefully implement the ISRs.

    Even though the codes are old and fully tested, I would like you to check the above once and revert back with the results.

    Regards,

    Gautam

  • Thanks for yoyr reply,

      Below code is working OK.


        //IntEnable(INT_TIMER0A);
        IntEnable(INT_TIMER1A);
        IntEnable(INT_UART0);
        IntEnable(INT_UART1);
        IntEnable(INT_UART3);
        IntEnable(INT_SSI0);

    But as i add line

        VCC_RDY_EN;

        IntEnable(INT_TIMER0A);

    code goes into fault ISR.

    Following is my cmd file.

    /*
    //###########################################################################
    // FILE:    F28M35x_generic_M3_FLASH.cmd
    // TITLE:   Linker Command File for F28M35x examples that run out of FLASH
    //###########################################################################
    // $TI Release: F28M35x Support Library v140 $
    // $Release Date: Tue Jul  3 09:38:11 CDT 2012 $
    //###########################################################################
    */

    --retain=g_pfnVectors

    /* The following command line options are set as part of the CCS project.    */
    /* If you are building using the command line, or for some reason want to    */
    /* define them here, you can uncomment and modify these lines as needed.     */
    /* If you are using CCS for building, it is probably better to make any such */
    /* modifications in your CCS project and leave this file alone.              */
    /*                                                                           */
    /* --heap_size=0                                                             */
    /* --stack_size=256                                                          */
    /* --library=rtsv7M3_T_le_eabi.lib                                           */


    /* The following options allow the user to program Z1 and Z2 DCSM security   */
    /* values, include CSM PSWD, ECSL PSWD, GRABSECT, GRABRAM, and FLASH EXEONLY */
    /* The driverlib/dcsm_z1_secvalues.s and driverlib/dcsm_z2_secvalues.s files */
    /* must be included in the Flash project for the below 2 lines to take       */
    /* effect.                                                                   */
    --retain=dcsm_z1_secvalues.obj(.z1secvalues,.z1_csm_rsvd)
    --retain=dcsm_z2_secvalues.obj(.z2secvalues,.z2_csm_rsvd)

    /* System memory map */

    MEMORY
    {
        CSM_ECSL_Z1     : origin = 0x00200000, length = 0x0024
        CSM_RSVD_Z1     : origin = 0x00200024, length = 0x000C
        RESETISR (RX)   : origin = 0x00200030, length = 0x0008   /* Reset ISR is mapped to boot to Flash location */
        INTVECS (RX)    : origin = 0x00201000, length = 0x01B0
        FLASHLOAD (RX)  : origin = 0x00201200, length = 0x2E00   /* For storing code in Flash to copy to RAM at runtime */
        FLASH1 (RX)     : origin = 0x00204000, length = 0x1C000
        FLASH2 (RX)     : origin = 0x00260000, length = 0x1FF00
        CSM_RSVD_Z2     : origin = 0x0027FF00, length = 0x00DC
        CSM_ECSL_Z2     : origin = 0x0027FFDC, length = 0x0024
        C0 (RWX)        : origin = 0x20000000, length = 0x2000
        C1 (RWX)        : origin = 0x20002000, length = 0x2000
        BOOT_RSVD (RX)  : origin = 0x20004000, length = 0x0900
        C2 (RWX)        : origin = 0x20004900, length = 0x1700
        C3 (RWX)        : origin = 0x20006000, length = 0x2000
        CTOMRAM (RX)    : origin = 0x2007F000, length = 0x0800
        MTOCRAM (RWX)   : origin = 0x2007F800, length = 0x0800
    }

    /* Section allocation in memory */

    SECTIONS
    {
        .intvecs:   > INTVECS
        .resetisr:  > RESETISR
        .text   :   >> FLASH1 | FLASH2
        .const  :   >> FLASH1 | FLASH2
        .cinit  :   >  FLASH1 | FLASH2
        .pinit  :   >> FLASH1 | FLASH2

        .vtable :   >  C0 | C1 | C2 | C3
        .data   :   >  C2 | C3
        .bss    :   >> C2 | C3
        .sysmem :   >  C0 | C1 | C2 | C3
        .stack  :   >  C0 | C1 | C2 | C3
        
        .z1secvalues  :   >  CSM_ECSL_Z1
        .z1_csm_rsvd  :   >  CSM_RSVD_Z1
        .z2secvalues  :   >  CSM_ECSL_Z2
        .z2_csm_rsvd  :   >  CSM_RSVD_Z2
        
        
         ramfuncs            : LOAD = FLASHLOAD,
                               RUN = C0,
                               LOAD_START(RamfuncsLoadStart),
                               LOAD_SIZE(RamfuncsLoadSize),
                               RUN_START(RamfuncsRunStart),
                               PAGE = 0
        
        GROUP : > MTOCRAM
        {
            PUTBUFFER  
            PUTWRITEIDX
            GETREADIDX  
        }

         GROUP : > CTOMRAM
        {
            GETBUFFER : TYPE = DSECT
            GETWRITEIDX : TYPE = DSECT
            PUTREADIDX : TYPE = DSECT
        }    
    }