Problem with Concerto F28M35xx (rev b) controlCARD and ethernet

Hi Davide,

while there is not any answer, just in case, I would wish clarify something. If I understand, you have added already these files:

//###########################################################################
// FILE:   set_pinout_f28m35x.c
// TITLE:  GPIO setup for the F28M35x controlCARD.
//###########################################################################
// $TI Release: F28M3Xx Driver Library vAlpha1 $
// $Release Date: February 27, 2012 $
//###########################################################################

#include "inc/hw_gpio.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/epi.h"
#include "driverlib/gpio.h"
#include "driverlib/i2c.h"
#include "driverlib/rom.h"
#include "driverlib/sysctl.h"
#include "board_drivers/set_pinout_f28m35x.h"

//*****************************************************************************
//
//! \addtogroup set_pinout_api
//! @{
//
//*****************************************************************************



//*****************************************************************************
//
// Set the GPIO port control registers appropriately for the hardware.
//
// This function determines the correct port control settings to enable the
// basic peripheral signals for the development board on their respective pins
// and also ensures that all required EPI signals are correctly routed.  The
// EPI signal configuration is determined from the daughter board information
// structure passed via the \e psInfo parameter.
//
//*****************************************************************************
static void
PortControlSet(void)
{
   
    //
    // To begin with, we set the port control values for all the non-EPI
    // peripherals.
    //


    //UART Setup
    GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_4 | GPIO_PIN_5);
    GPIOPinConfigure(GPIO_PE4_U0RX);
    GPIOPinConfigure(GPIO_PE5_U0TX);
    
    //SSI SD Card Setup
    GPIOPinTypeSSI(SDC_GPIO_PORT_BASE, SDC_SSI_TX | SDC_SSI_RX | SDC_SSI_CLK);
    GPIOPinTypeGPIOOutput(SDCARD_CS_BASE, SDCARD_CS_PIN);
    GPIOPadConfigSet(SDC_GPIO_PORT_BASE, SDC_SSI_PINS,
                     GPIO_PIN_TYPE_STD_WPU);
    GPIOPadConfigSet(SDCARD_CS_BASE, SDCARD_CS_PIN,
                     GPIO_PIN_TYPE_STD_WPU);
    GPIOPinConfigure(GPIO_PD0_SSI0TX);
    GPIOPinConfigure(GPIO_PD1_SSI0RX);
    GPIOPinConfigure(GPIO_PD2_SSI0CLK);
    GPIOPinWrite(SDCARD_CS_BASE, SDCARD_CS_PIN, SDCARD_CS_PIN);


    // USB Pins
    GPIOPinConfigure(GPIO_PC5_USB0EPEN);
    GPIOPinConfigure(GPIO_PJ1_USB0PFLT);
    GPIOPinTypeUSBDigital(GPIO_PORTC_BASE, GPIO_PIN_5);
    GPIOPinTypeUSBDigital(GPIO_PORTJ_BASE, GPIO_PIN_1);
    GPIOPinTypeUSBAnalog(GPIO_PORTF_BASE, GPIO_PIN_6);
    GPIOPinTypeUSBAnalog(GPIO_PORTG_BASE, GPIO_PIN_2 | GPIO_PIN_5 | GPIO_PIN_6);


    //Ethernet pin setup
    GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD);
    GPIOPinConfigure(GPIO_PC4_MIITXD3);

    GPIODirModeSet(GPIO_PORTE_BASE, GPIO_PIN_6, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTE_BASE, GPIO_PIN_6, GPIO_PIN_TYPE_STD);
    GPIOPinConfigure(GPIO_PE6_MIIMDIO);

    GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_5, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_5, GPIO_PIN_TYPE_STD);
    GPIOPinConfigure(GPIO_PF5_MIIRXD3);

    GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_7|GPIO_PIN_3|GPIO_PIN_1|GPIO_PIN_0,
                   GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_7|GPIO_PIN_3|GPIO_PIN_1|
                     GPIO_PIN_0,
                     GPIO_PIN_TYPE_STD);
    GPIOPinConfigure(GPIO_PG0_MIIRXD2);
    GPIOPinConfigure(GPIO_PG1_MIIRXD1);
    GPIOPinConfigure(GPIO_PG3_MIIRXDV);
    GPIOPinConfigure(GPIO_PG7_MIITXER);

    GPIODirModeSet(
        GPIO_PORTH_BASE, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4|
        GPIO_PIN_3|
        GPIO_PIN_1, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(
        GPIO_PORTH_BASE, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4|
        GPIO_PIN_3|
        GPIO_PIN_1, GPIO_PIN_TYPE_STD);
    GPIOPinConfigure(GPIO_PH1_MIIRXD0);
    GPIOPinConfigure(GPIO_PH3_MIITXD2);
    GPIOPinConfigure(GPIO_PH4_MIITXD1);
    GPIOPinConfigure(GPIO_PH5_MIITXD0);
    GPIOPinConfigure(GPIO_PH6_MIITXEN);
    GPIOPinConfigure(GPIO_PH7_MIITXCK);

    GPIODirModeSet(
        GPIO_PORTJ_BASE, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4|
        GPIO_PIN_3|
        GPIO_PIN_2|GPIO_PIN_0, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(
        GPIO_PORTJ_BASE, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4|
        GPIO_PIN_3|
        GPIO_PIN_2|GPIO_PIN_0, GPIO_PIN_TYPE_STD);
    GPIOPinConfigure(GPIO_PJ0_MIIRXER);
    GPIOPinConfigure(GPIO_PJ2_MIIRXCK);
    GPIOPinConfigure(GPIO_PJ3_MIIMDC);
    GPIOPinConfigure(GPIO_PJ4_MIICOL);
    GPIOPinConfigure(GPIO_PJ5_MIICRS);
    GPIOPinConfigure(GPIO_PJ6_MIIPHYINTRn);
    GPIOPinConfigure(GPIO_PJ7_MIIPHYRSTn);


}

//*****************************************************************************
//
//! Configures the device pinout for the development board.
//!
//! This function configures each pin of the device to route the! appropriate
//! peripheral signal as required by the design of the development board.
//!
//! \note This module can be built in two ways.  If the label SIMPLE_PINOUT_SET
//! is not defined, the PinoutSet() function will attempt to read an I2C EEPROM
//! to determine which daughter board is attached to the development kit board
//! and use information from that EEPROM to dynamically configure the EPI
//! appropriately.  In this case, if no EEPROM is found, the EPI configuration
//! will default to that required to use the SDRAM daughter board which is
//! included with the base development kit.
//!
//! If SIMPLE_PINOUT_SET is defined, however, all the dynamic configuration
//! code is replaced with a very simple function which merely sets the pinout
//! and EPI configuration statically.  This is a better representation of how a
//! real-world application would likely initialize the pinout and EPI timing
//! and takes significantly less code space than the dynamic, daughter-board
//! detecting version.  The example offered here sets the pinout and EPI
//! configuration appropriately for the Flash/SRAM/LCD daughter board.
//!
//! \return None.
//
//*****************************************************************************
void
PinoutSet(void)
{
    
    //
    // Enable all GPIO banks.
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);

    //
    // Determine the port control settings required to enable the EPI pins
    // and other peripheral signals for this daughter board and set all the
    // GPIO port control registers.
    //
    PortControlSet();

}

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

8233.set_pinout_f28m35x.h

and this inclusion in enet_uip.c: 

#include "set_pinout_f28m35x.h"

Is not it?

Regards,

Igor

Yes, this is what I did... without success. Before this fix, the green led on ethernet input was not able to blink. Now it blink correctly but code execution hangs in that "while".

Another info: I'm using CCS v5.5 with TI compiler v5.1.1.

There may be an issue on DMA handling?

Davide,

and what about "MII_PHYRST problem"? If  I understand, for fixing this problem at revision 0 "additional efforts" should be taken according Silicon Errata SPRZ357G. Starting with revision A this problem was fixed and these "additional efforts" are not needed now. Perhaps I'm wrong, and it doesn't matter, but maybe it makes sense to revise your code for revision B in this aspect.

Regards,

Igor

Igor, thanks for your support. I well know that I must revise my code... the problem is that not even the original enet_uip_m3 example works on the rev b chip! The situation is:

- original enet_uip_m3 v201 on rev 0 chip: works;

- original enet_uip_m3 v201 on rev b chip: doesn't work, the ethernet green led is not blinking and the program always awaits for the link to become active;

- enet_uip_m3 v201 with pinout fix on rev b chip: doesn't work, the ethernet green led is blinking but the program awaits eternally on the "while" of the first post;

- enet_lwip_m3 v201 with pinout fix on rev b chip: works;

Do you need any additional information?

Davide,

would you like to try original enet_uip of V160 from this thread http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/295531.aspx?pi269061=2 (refer please to post "verified answer") with addition of pinout fix or did you try it already?

Regards,

Igor

Yes, I've already tried enet_uip_m3 v160 with and without pinout fix. Of course it doesn't work.

---UPDATE---

Finally I can see the demo web page on my browser with enet_uip_m3 v201 example... The solution is to use ethernet Get and Put without uDMA controller.

Unfortunately I need uDMA because in my program the M3 core does a lot of real-time requests to C28 core and handles continuously communications with LIN and SCI.

Now I know that the problem is inside the uDMA handling and I can focus on it.

What's changed in the uDMA handling from rev 0 to rev b?

Well, let's wait for explanation of TI employees...

Igor

We need help for this issue!

Davide,

apologize for the delay. There is a change with respect to how uDMA SW channel is used by peripheral for data transfer after REV0. on REV0 end of transfer interrupt was generated on the peripheral interrupt line but from REVA onwards the end of transfer is being generated on the uDMA interrupt line.

The ControlSuite EMAC uDMA example hasn't been updated for that change yet. You should see it in the next update, but below is the change you need to make in the example - add the code in GREEN after the CODE in YELLOW in your example code.

  // Enable and register the Ethernet interrupt.

   IntRegister(INT_ETH, EthernetIntHandler);    

    IntEnable(INT_ETH);

    IntRegister(INT_UDMA, EthernetIntHandler);    

    IntEnable(INT_UDMA);

hope it helps...please let us know if you have any questions.

Best Regards

Santosh

Hi Santosh, thanks for the hint. Now the program flow runs correctly (uDMA interrupt fixed) but I can't see any in/out TCP or UDP traffic. I've verified this with a network sniffer.

Any idea?

It could be that your device is not getting the IP address, are you using static or dynamic ip. Also take a look at the documentation provided in controlsuite for your device - C:\ti\controlSUITE\device_support\f28m35x\v201\doc

Best regards

Santosh

It doesn't work neither with static IP nor with dhcp. We've tried also with a one-to-one cross link with my pc... fails. The control card seems to be isolated from tcp/udp world, it never stops with a ethernet RX interrupt!
The same code (without last uDMA fix) works well on silicon rev 0.

We have tight deadlines to deliver the products to our customers, and we begin to be tired of using this chip...

This is my actual main configuration:

    volatile unsigned long ulLoop;
    
    uip_ipaddr_t ipaddr;
    static struct uip_eth_addr sTempAddr;
    long lPeriodicTimer, lARPTimer;
    unsigned long ulUser0, ulUser1;
    unsigned long ulTemp;
    int command_word;

    // Disable Protection
    HWREG(SYSCTL_MWRALLOW) =  0xA5A5A5A5;
    
    // Tells M3 Core the vector table is at the beginning of C0 now.
    HWREG(NVIC_VTABLE) = 0x20005000;

    // Setup main clock tree for 75MHz - M3 and 150MHz - C28x
    SysCtlClockConfigSet(SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_2 | SYSCTL_USE_PLL |
                         (SYSCTL_SPLLIMULT_M & 0x0F));

/*
     // Sets up PLL, M3 running at 100MHz and C28 running at 100MHz
    SysCtlClockConfigSet(SYSCTL_USE_PLL | (SYSCTL_SPLLIMULT_M & 0xA) |
                         SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_1 |
                         SYSCTL_XCLKDIV_4);
*/
    // Enable clock supply for GPIOC
    // Enable all GPIOs
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
    
  
    GPIOPinConfigureCoreSelect(GPIO_PORTA_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);
    GPIOPinConfigureCoreSelect(GPIO_PORTB_BASE, 0x01, GPIO_PIN_C_CORE_SELECT);  
    GPIOPinConfigureCoreSelect(GPIO_PORTC_BASE, 0xC0, GPIO_PIN_C_CORE_SELECT);
    GPIOPinConfigureCoreSelect(GPIO_PORTD_BASE, 0x01, GPIO_PIN_C_CORE_SELECT);
    GPIOPinConfigureCoreSelect(GPIO_PORTE_BASE, 0x30, GPIO_PIN_C_CORE_SELECT);
    GPIOPinConfigureCoreSelect(GPIO_PORTF_BASE, 0x03, GPIO_PIN_C_CORE_SELECT);
   
    GPIOPadConfigSet(GPIO_PORTA_BASE, 0xFF, GPIO_PIN_TYPE_STD_WPU);
    GPIOPadConfigSet(GPIO_PORTB_BASE, 0x01, GPIO_PIN_TYPE_STD_WPU);   
    GPIOPadConfigSet(GPIO_PORTC_BASE, 0xC0, GPIO_PIN_TYPE_STD_WPU); 
    GPIOPadConfigSet(GPIO_PORTD_BASE, 0x01, GPIO_PIN_TYPE_STD_WPU); 
    GPIOPadConfigSet(GPIO_PORTE_BASE, 0x30, GPIO_PIN_TYPE_STD_WPU);
    GPIOPadConfigSet(GPIO_PORTF_BASE, 0x03, GPIO_PIN_TYPE_STD_WPU);
    
    EthernetPinsSetup(); // TI fixed

    // Set GPIO E4 and E5 as UART pins.    
    /*
    GPIOPinTypeUART(GPIO_PORTB_BASE, GPIO_PIN_3 | GPIO_PIN_1);
    GPIOPinConfigure(GPIO_PB3_U1RX);
    GPIOPinConfigure(GPIO_PB1_U1TX);
    
    GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_4 | GPIO_PIN_5);
    GPIOPinConfigure(GPIO_PE4_U0RX);
    GPIOPinConfigure(GPIO_PE5_U0TX);*/
    
    // Set up LED6 pin
    GPIOPinTypeGPIOOutput(GPIO_PORTC_BASE, GPIO_PIN_7);
    GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0);

    // Set up LED7 pin
    GPIOPinTypeGPIOOutput(GPIO_PORTC_BASE, GPIO_PIN_7);
    GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0);
   
    // Adjust the pointer to be aligned on an odd half word address so that
    // DMA can be used.
    uip_buf = (u8_t *)(((unsigned long)ucUIPBuffer + 3) & 0xfffffffe);

    // Enable the uDMA controller and set up the control table base.
    SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
    uDMAEnable();
    uDMAControlBaseSet(g_sDMAControlTable);

    // Configure the DMA TX channel
    uDMAChannelAttributeDisable(UDMA_CHANNEL_ETH0TX, UDMA_ATTR_ALL);
    uDMAChannelControlSet(UDMA_CHANNEL_ETH0TX,
                          UDMA_SIZE_32 | UDMA_SRC_INC_32 |
                          UDMA_DST_INC_NONE | UDMA_ARB_8);

    // Set user/company specific MAC octates.
    // (for this code we are using A8-63-F2-00-00-80)
    // 0x00 MACOCT3 MACOCT2 MACOCT1
    ulUser0 = 0x00F263A8;
    ulUser1 = 0x00FD0F00;
    // User needs to program user specific MAC address into Flash
    // and read it on power up
    if((ulUser0 == 0xffffffff) || (ulUser1 == 0xffffffff))
    {
        // We should never get here.  This is an error if the MAC address has
        // not been programmed into the device.  Exit the program.
        while(1)
        {
        }
    }
    
    // Enable and Reset the Ethernet Controller.
    SysCtlPeripheralEnable(SYSCTL_PERIPH_ETH);
    SysCtlPeripheralReset(SYSCTL_PERIPH_ETH);

    // Configure SysTick for a periodic interrupt.
    SysTickPeriodSet(SysCtlClockGet(SYSTEM_CLOCK_SPEED) / SYSTICKMS);
    SysTickEnable();
    IntRegister(FAULT_SYSTICK, SysTickIntHandler);
    SysTickIntEnable();


    // Configure the DMA channel for Ethernet receive.
    uDMAChannelAttributeDisable(UDMA_CHANNEL_ETH0RX, UDMA_ATTR_ALL);
    uDMAChannelControlSet(UDMA_CHANNEL_ETH0RX,
                          UDMA_SIZE_32 | UDMA_SRC_INC_NONE |
                          UDMA_DST_INC_32 | UDMA_ARB_8);

    // Initialize the Ethernet Controller and disable all Ethernet Controller
    // interrupt sources.
    EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO |
                                  ETH_INT_RXER | ETH_INT_RXOF |
                                  ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));
    ulTemp = EthernetIntStatus(ETH_BASE, false);
    EthernetIntClear(ETH_BASE, ulTemp);

    // Initialize the Ethernet Controller for operation.
    EthernetInitExpClk(ETH_BASE, SysCtlClockGet(SYSTEM_CLOCK_SPEED));

    // Configure the Ethernet Controller for normal operation.
    // - Full Duplex
    // - TX CRC Auto Generation
    // - TX Padding Enabled
    EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN |
                                 ETH_CFG_TX_PADEN));

    // Wait for the link to become active.
    while((EthernetPHYRead(ETH_BASE, PHY_MR1) & 0x0004) == 0)
    {
    }

    // Enable the Ethernet Controller.
    EthernetEnable(ETH_BASE);
    
    // Enable and register the Ethernet interrupt.
    IntRegister(INT_ETH, EthernetIntHandler);
    IntEnable(INT_ETH);

#ifdef DMA_ENABLE
    // 04122013 TI FIX (enable uDMA interrupt)
    IntRegister(INT_UDMA, EthernetIntHandler);
    IntEnable(INT_UDMA);
#endif

    // Enable the Ethernet RX Packet interrupt source.
    EthernetIntEnable(ETH_BASE, ETH_INT_RX);

    // Initialize the uIP TCP/IP stack.
    uip_init();
#ifdef USE_STATIC_IP
    uip_ipaddr(ipaddr, DEFAULT_IPADDR0, DEFAULT_IPADDR1, DEFAULT_IPADDR2,
               DEFAULT_IPADDR3);
    uip_sethostaddr(ipaddr);

    uip_ipaddr(ipaddr, DEFAULT_IPADDR0, DEFAULT_IPADDR1, DEFAULT_IPADDR2,1);
    uip_setdraddr(ipaddr);
    //ShowIPAddress(ipaddr);
    uip_ipaddr(ipaddr, DEFAULT_NETMASK0, DEFAULT_NETMASK1, DEFAULT_NETMASK2,
               DEFAULT_NETMASK3);
    uip_setnetmask(ipaddr);
#else
    uip_ipaddr(ipaddr, 0, 0, 0, 0);
    uip_sethostaddr(ipaddr);
    uip_ipaddr(ipaddr, 0, 0, 0, 0);
    uip_setnetmask(ipaddr);
#endif

    // Convert the 24/24 split MAC address from ram into a 32/16 split MAC
    // address needed to program the hardware registers, then program the MAC
    // address into the Ethernet Controller registers.
    sTempAddr.addr[0] = ((ulUser0 >>  0) & 0xff);
    sTempAddr.addr[1] = ((ulUser0 >>  8) & 0xff);
    sTempAddr.addr[2] = ((ulUser0 >> 16) & 0xff);
    sTempAddr.addr[3] = ((ulUser1 >>  0) & 0xff);
    sTempAddr.addr[4] = ((ulUser1 >>  8) & 0xff);
    sTempAddr.addr[5] = ((ulUser1 >> 16) & 0xff);

    // Program the hardware with it's MAC address (for filtering).
    EthernetMACAddrSet(ETH_BASE, (unsigned char *)&sTempAddr);
    uip_setethaddr(sTempAddr);

    // Initialize the TCP/IP Application (e.g. web server).
    httpd_init();
    udpOstis_init();
#ifndef USE_STATIC_IP

    // Initialize the DHCP Client Application.
    dhcpc_init(&sTempAddr.addr[0], 6);
    dhcpc_request();
#endif

    // Main Application Loop.
    lPeriodicTimer = 0;
    lARPTimer = 0;
    httpd_clear_command();

    MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);   
    // Call Flash Initialization to setup flash waitstates
    // This function must reside in RAM
    FlashInit();  
    
    SysCtlReleaseSubSystemFromReset(SYSCTL_CONTROL_SYSTEM_RES_CNF);	 
             
    master_ram_init_control_m0m1_msgram_memories();
    master_ram_init_control_L0_L4_memories();
    //Init System Variable
    Init_GUI_Variable(); 
    
    RamMReqSharedMemAccess((S6_ACCESS),C28_MASTER);
    RamMReqSharedMemAccess((S7_ACCESS),M3_MASTER);    

	// assign S0 and S1 of the shared ram for use by the c28
    // Details of how c28 uses these memory sections is defined 
    // in the c28 linker file.(28M35H52C1_RAM_lnk.cmd)

    IPCMtoCBootControlSystem(CBROM_MTOC_BOOTMODE_BOOT_FROM_FLASH);

    // Disable clock supply for the watchdog modules
    SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG1);
    SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG0);
      
    // Enable processor interrupts.
    IntMasterEnable();

Please provide help.

Hi Davide,

I'm not sure, but perhaps you will find something useful at that thread http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/285441.aspx?pi269061=1

(although it refers to M36)

Regards,

Igor

Thanks Igor, I have already seen your post but without any useful info. Do you have tried the enet_uip v201 example with ethernet and uDMA with rev b silicon?

If yes and if is working, please provide me the full fixed project.

Best regards.

Davide,

in your wireshark logs do you see any DHCP packets from the device at all (when you configure the example for Dynamic IP)? if not try disabling antivirus or windows firewall for a minute and see.

Have a test laptop directly connected to the device using a straight cable and run the packet sniffer on the test laptop to be sure that the packets are not dropped at any other switch/hub/router in the network.

it still beats me why it would work without UDMA, the uDMA example with suggested modifications is tested by the team though and found to be working, I will check with my team mate again.

Best Regards

Santosh

Davide,

Here is the full project I just tested and validated using Rev B and the modification to the uDMA Santosh mentioned.

I tested it with both static IP and DHCP settings. It works. If yo uare using the static IP option on windows 7 or later OS change the TCP/IPv4 setting.

Thanks

Noah

0576.enet_uip.zip