SCI FIFO Tx Interrupt flag is always set

In continuation to previous issue:

When I clear interrupt occurrence bit every time TXBUFF is written. We need to write it 4 times in tx interrupt to fill the FIFO buffer completely.

SciaRegs.SCIFFTX.bit.TXFFINTCLR = 1;

It works almost. I get factor of 3.9 (factor of data vs. interrupt occurrence). But I dont understand why? If someone can help.

2. I am still missing every 5th byte in continuous transmission.

-Varun

The TX interrupt will remain active as long as the TX fifo is empty.  If you are not transmitting data, the Tx interrupt must be disabled (TXFFIENA = 0).

Hi Greg,

Yes. you are right, but issue here was different.

Solution: we need to add little delay after clearing INTFlag, so it has time before another instance of interrupt hits. After I add small delay, it works.

btw, I still have reception issue. I am missing every 5th byte on receive side (FIFO buffer is set to 4), during debugging, I can see that value is reaching till RXBUFF but it is missed during copying. any hints there???

Can someone from TI specify this hardware delay (to make sure CLR instruction is reflected on HW) needed for chip tms320f28069 ?

because I dont want to put extra wait cycles at end of ISR, instead would like to use clock spend of ISR instruction as wait cycles also.

Varun Kumar3 said:

Hi Greg,

Yes. you are right, but issue here was different.

Solution: we need to add little delay after clearing INTFlag, so it has time before another instance of interrupt hits. After I add small delay, it works.

btw, I still have reception issue. I am missing every 5th byte on receive side (FIFO buffer is set to 4), during debugging, I can see that value is reaching till RXBUFF but it is missed during copying. any hints there???

TX: I suppose the IFR is set agin since the interrupt source is always active, so You can try with the following sequence:

1. Clear the SCA INT flag

2. Ack the PIE Ctrl

3. Clear the IFR (AND IFR, #xxx)

RX: if you set the level to 4, the FIFO is full when you service the interrupts. If meanwhile another char arrive, there is no room on the fifo to store it. Try to set FIFO level to 3.

Hi Alberto,

I see in manual they have said, "Never to clearn IFR bit manually and shall be done via HW only". Btw, for experiment purpose I will try it.

Regarding RX: I had tried for FIFO level 3, then one byter after each 3rd byte is being missed and then same pattern repeats. 

I dont see it as FIFO buffer full issue, because 1st byte of pattern is being missed, and when I send first dummy byte and then 4 bytes then all 4 bytes are received correctly.

I think you should look at the use of the Receiver-buffer / Break interrupt.

The following sections in the SCI Reference Guide contain information about this feature:

1) section 1.2.8 SCI Port Interrupts

2) section 2.6 SCIRXST.BRKDT

3) section 2.3 SCICTL1.SWRESET

A few years ago, there was a lot of conversation in this forum about how this function worked or didn't (search the forums).  In the short time I worked on this I did not get it to work as an Idle Line interrupt.  The Break Interrupt features seem to be a little different.

Hope this helps,

Greg.

One thread of interest might be....

http://e2e.ti.com/support/microcontrollers/c2000/f/171/p/100750/547412.aspx#547412

Hello Varun,

For SciaRegs.SCIFFTX.all = 0xE020;

Have you tried different setting? For example: 0xE024 or 0xC024?

For SciaRegs.SCIFFRX.all = 0x2033; //0x2034; //0x0022;

This one for me is a little strange. What device that you use?

0x2033h = 00100000 00110011b --> bits 0-4 are used for Receive FIFO interrupt level bits ( RXFFIL4−0) and the maximum number is 4. So it should be 00100000 00100100b = 0x2024

Can you try to change these settings? And let us know the result.

Best regards,

Maria

OK, good to know you have solved it :)

Best regards,

Maria