C28x ADC Source Input Impedance

Hi Paul,

What is the maximum this value could be?

Any particular reason you're looking for the maximum value? Sticking around the typical value would yield you better results.

Regards,

Gautam

Paul,

The typical impedance roughly corresponds to the impedance needed to use the minimum S+H window and therefore achieve maximum possible sample rate.  When using higher source impedance, you can compensate by increasing the S+H window duration (increase ACQPS register setting).

The best way to approach this is to simulate the circuit in SPICE using the provided ADC model in the datasheet connected to a model of your driving circuit.  You want to ensure that the internal S+H capacitor can charge to within at least 1/2LSB of the final value in the allotted S+H duration.  

In addition to reducing the source impedance, you can also add a charge sharing capacitance on the pin.  This app. note will give you some idea how this works and how to calculate the desired capacitor size:

http://www.ti.com/lit/an/spna061/spna061.pdf  

Very helpful Devin!  Thanks!

I see in the datasheet that the minimum REFHI is 2.64V, and I was originally shooting for a 2.5V reference.  However, it looks like a 3.0V reference is in order.  I plan to bias the ADC Circuitry with 3.3V.  I do not want to overdrive the ADC input so I was thinking of biasing my last stage op-amp with 3.3V to limit any negative impact and give full input swings of 0V to 3V.

Would this be acceptable?

Thanks again!

Paul