Using a DRV8312-69M-KIT development kit.
Started with the ecan_back2back sample. Worked great. Commented out the self test code so that it went out externally. Had a separate device and application receiving and transmitting with the board. Worked great.
Commented out the receiving portion of the sample and implemented code to enable interrupts and install an ISR. I set a breakpoint in the ISR. My breakpoint never gets hit. I set a breakpoint in the for loop and I see CANRMP register is always 0. Is there something I forgot to turn on?
void main(void)
{
// eCAN control registers require read/write access using 32-bits. Thus we
// will create a set of shadow registers for this example. These shadow
// registers will be used to make sure the access is 32-bits and not 16.
struct ECAN_REGS ECanaShadow;
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2806x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initalize GPIO:
// This example function is found in the F2806x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// For this example, configure CAN pins using GPIO regs here
// This function is found in F2806x_ECan.c
InitECanGpio();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2806x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2806x_DefaultIsr.c.
// This function is found in F2806x_PieVect.c.
// InitPieVectTable();
// Step 4. Initialize all the Device Peripherals:
// This function is found in F2806x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
// Step 5. User specific code, enable interrupts:
InitECana(); // Initialize eCAN-A module
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.ECAN1INTA = &ecan1intA_isr; // re-map CAN INT1
// PieVectTable.ECAN0INTA = &ecan0intA_isr; // re-map CAN INT1
/* mailbox interrupt mask */
/* 1 = interrupt enabled */
ECanaRegs.CANMIM.all = 0xFFFFFFFF;
/* mailbox interrupt level */
/* mailbox inerrupt is generated on interrupt line 1. */
ECanaRegs.CANMIL.all = 0xFFFFFFFF;
/* Global Interrupt Mask Register */
ECanaShadow.CANGIM.all = 0;
ECanaShadow.CANGIM.bit.AAIM = 1; /* Abort acknowledge */
ECanaShadow.CANGIM.bit.WDIM = 1; /* Write denied */
ECanaShadow.CANGIM.bit.WUIM = 1; /* Wake up */
ECanaShadow.CANGIM.bit.BOIM = 1; /* Bus-off */
ECanaShadow.CANGIM.bit.EPIM = 1; /* Error-passive */
ECanaShadow.CANGIM.bit.WLIM = 1; /* Warining level */
ECanaShadow.CANGIM.bit.I1EN = 1; /* Interrupt 1 enable */
ECanaShadow.CANGIM.bit.GIL = 1; /* Global Interrup Level. */
// ECanaShadow.CANGIM.bit.I0EN = 1; /* Interrupt 0 enable */
// ECanaShadow.CANGIM.bit.GIL = 0; /* Global Interrup Level. */
ECanaShadow.CANGIM.bit.RMLIM = 1; /* Received Messae Lost */
ECanaRegs.CANGIM.all = ECanaShadow.CANGIM.all;
EDIS; // This is needed to disable write to EALLOW protected registers
// Mailboxs can be written to 16-bits or 32-bits at a time
// Write to the MSGID field of TRANSMIT mailboxes MBOX0 - 15
// using extended ID's
// Write to the MSGID field of RECEIVE mailboxe MBOX16
ECanaMboxes.MBOX16.MSGID.all = 0x9555AAA0;
//ECanaLAMRegs.LAM16.all = 0xFFFFFFFF;
// Configure Mailboxes 0-15 as Tx, 16-31 as Rx
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
/* mailbox direction */
ECanaRegs.CANMD.all = 0xFFFF0000;
// Enable all Mailboxes */
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
/* mailbox enable */
ECanaRegs.CANME.all = 0xFFFFFFFF;
// Enable interrupts required for this example
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER9.bit.INTx5=1; // ECAN0INTA
PieCtrlRegs.PIEIER9.bit.INTx6=1; // ECAN1INTA
IER = 0x0101; // enable core line INT1
EINT; //enable global interrupt INTM
ERTM; // enable global real time dbgm
EnableInterrupts();
// Begin transmitting
for(;;)
{
asm (" NOP");
// mailbox_read(16);
}
}
__interrupt void ecan1intA_isr(void)
{
unsigned int mailbox_nr;
mailbox_nr = ECanaRegs.CANGIF1.bit.MIV1;
if(mailbox_nr == 16)
{
ECanaRegs.CANRMP.bit.RMP16 = 1;
}
PieCtrlRegs.PIEACK.bit.ACK9|= 1; // Issue PIE ack
IER |= 0x0100;
EINT;
}
__interrupt void ecan0intA_isr(void)
{
unsigned int mailbox_nr;
mailbox_nr = ECanaRegs.CANGIF1.bit.MIV1;
if(mailbox_nr == 16)
{
ECanaRegs.CANRMP.bit.RMP16 = 1;
}
PieCtrlRegs.PIEACK.bit.ACK9|= 1; // Issue PIE ack
IER |= 0x0100;
EINT;
}
but the breakpoint never gets hit. Any ideas? I tried Int 0 as well as Int 1.
