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F2803x Phase shift

Edwin.Liu
Intellectual 600 points


Dear all:

               I am working on a project using F28035 to control interleave boost. EPWM1&2 are the main channel, and EPWM3&4 are phase *** 180 degree. when the duty  changing from less than 50% to large than 50%, EPWM3&4 will lose one period pwm as showed in the picture.

The Channel 4 in the picture is EPWM1, and the channel 3 is EPWM3.

Please help, thanks.

  • 0
    Intellectual 600 points

    here is my configuration.

    void InitUserEPwm1(int period)
    {
    EALLOW;
    SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1 clock


    EPwm1Regs.AQSFRC.bit.RLDCSF = 1; //AQCSFRC Active Register Reload From Shadow Options Load on event counter equals zero
    EPwm1Regs.AQCSFRC.all = 0x1; //PWM1A force low

    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set shadow load
    EPwm1Regs.TBPRD = period - 1; // PWM period
    EPwm1Regs.CMPA.half.CMPA = 0;
    EPwm1Regs.CMPA.half.CMPAHR = 0;
    EPwm1Regs.TBPHS.all = 0;

    EPwm1Regs.TBCTR = 0;
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //EPWMxSYNCO signal output when CTR=0
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.FREE_SOFT = 11;

    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;


    //EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A
    //EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
    EPwm1Regs.AQCTLA.all = 0x12;

    EPwm1Regs.ETSEL.bit.INTEN = 0; // Disable INT

    EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
    EPwm1Regs.ETSEL.bit.SOCASEL = 1; // Enable event time-base counter equal to TBCTR = 0x0000
    EPwm1Regs.ETPS.bit.SOCAPRD = 2; // Generate pulse on 2st ev
    //For Trip Zone

    EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_COMP1OUT; // DCBH = COMP1OUT
    EPwm1Regs.DCTRIPSEL.bit.DCBLCOMPSEL = DC_COMP2OUT; // DCBL = COMP2OUT
    EPwm1Regs.DCBCTL.bit.EVT2SRCSEL = DC_EVT2; // DCBEVT2 = DCBEVT2 (not filtered)
    EPwm1Regs.DCBCTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; // Take async path
    EPwm1Regs.TZDCSEL.bit.DCBEVT2 = 0x2; //DCAL = high ; DCAH don't care
    EPwm1Regs.TZSEL.bit.DCBEVT2 = 0x1; //EnableDCBEVT1asone-shot-tripsourcefor this ePWMmodule.

    EPwm1Regs.TZSEL.bit.CBC1 = TZ_ENABLE; // Enable TZ1 as one cycle-by-cycle trip sources
    EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // What do we want the TZ1 to do?

    EDIS;
    }

    void InitUserEPwm3(int period)
    {
    EALLOW;
    SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
    EPwm3Regs.AQSFRC.bit.RLDCSF = 1; //AQCSFRC Active Register Reload From Shadow Options Load on event counter equals zero
    EPwm3Regs.AQCSFRC.all = 0x1; //PWM1A force low

    EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set shadow load
    EPwm3Regs.TBPRD = period-2; // PWM period
    EPwm3Regs.CMPA.half.CMPA = 0;
    EPwm3Regs.CMPA.half.CMPAHR = 0;
    EPwm3Regs.TBPHS.half.TBPHS = (EPwm3Regs.TBPRD) >> 1; // Phase = 180 deg
    EPwm3Regs.TBPHS.half.TBPHSHR = 0;

    EPwm3Regs.TBCTR = 0;
    EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //EPWMxSYNCO signal output when CTR=0
    EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP; // Count DOWN on sync (=90 deg)
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm3Regs.TBCTL.bit.FREE_SOFT = 11;

    EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
    EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;


    //EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM3A
    //EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET;
    EPwm3Regs.AQCTLA.all = 0x12;
    EPwm3Regs.ETSEL.bit.INTEN = 0; // Disable INT

    //For Trip Zone

    EPwm3Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_COMP1OUT; // DCBH = COMP1OUT
    EPwm3Regs.DCTRIPSEL.bit.DCBLCOMPSEL = DC_COMP3OUT; // DCBL = COMP2OUT
    EPwm3Regs.DCBCTL.bit.EVT2SRCSEL = DC_EVT2; // DCBEVT2 = DCBEVT2 (not filtered)
    EPwm3Regs.DCBCTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; // Take async path
    EPwm3Regs.TZDCSEL.bit.DCBEVT2 = 0x2; //DCAH = high ; DCAL don't care
    EPwm3Regs.TZSEL.bit.DCBEVT2 = 0x1; //EnableDCBEVT1asone-shot-tripsourcefor this ePWMmodule.


    EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // What do we want the TZ1 to do?

    EDIS;

    }

    I found a method in other post.

    Making EPwm3Regs.TBPRD = EPwm1Regs.TBPRD - 1,

    But  It has no effect.

  • 0
    Guru 192875 points

    Hi Edwin,

    Try with this code:

    // Initialization Time
// = = = = = = = = = = = = = = = = = = = = = = = =
EPwm1Regs.TBPRD = 600; // Period = 2´600 TBCLK counts
EPwm1Regs.CMPA.half.CMPA = 300;
EPwm1Regs.CMPB = 300; 
EPwm1Regs.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTR = 0; // clear TB counter
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetric
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CBD = AQ_SET;
// Run Time
// = = = = = = = = = = = = = = = = = = = = = = = =
EPwm1Regs.CMPA.half.CMPA = 300; // adjust duty for output EPWM1A
EPwm1Regs.CMPB = 300; // adjust duty for output EPWM1B

    Do share your observations.

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Intellectual 600 points

    Thank you Gautam!

    I change my PWM mode to TB_COUNT_UPDOWN, then It works fine.

    Do you know why It do not work fine in TB_COUNT_UP mode?

  • 0 in reply to Edwin.Liu
    Guru 192875 points

    Edwin.Liu said:
    Do you know why It do not work fine in TB_COUNT_UP mode?

    Seems like a configuration issue; also lot of complications in the code. All you had to do is vary the action qualifiers ie AQCTL, that's it. You can try with the up count mode - following the same structure I provided above; simply vary the action qualifiers.

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Intellectual 600 points

    The structure is the same, but the up count mode still does not work fine.

    Thanks a lot.