TMS320F2801 SPI MAX transmission and recieve rate in master and slave mode

Oguzhan,

The maximum rate for both the master and slave will be LSPCLK/4 with the following limits:

"Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz 

In slave mode, the SPI module must synchronize with the incoming SPICLK, receive, and send data. Because the F2801 has no control over the incoming Clock, there will be some delays while the slave module synchronizes preventing the module from achieving 25-MHz.

Hey Mark,

Thank you for replying, but im a bit confused now, could you clarify it?

do you mean the maximum rate for the slave mode is LSPCLK/4 but  low speed prescaler must be adjusted to 50Mhz to keep slave mode recieve and send in 12.5Mhz Max ?

Oguzhan,

Mark is correct.  In SPI slave mode, the limit is the lesser of either 12.5 MHz, or LSPCLK/4.

Suppose for some reason you were only running the device at, say, SYSCLKOUT = 60 MHz (again, for whatever reason, maybe power consumption).  The default LSPCLK would be SYSCLKOUT/4 = 15 MHz, and you'd be limited to SPI slave clock at (15 MHz)/4 = 3.75 MHz.  If you adjusted the control bits so you had LSPCLK=SYSCLKOUT/1 = 60 MHz, you would then be limited to SPI slave clock of 12.5 MHz (because 60 MHz/4 = 15 MHz, but that is greater than the 12.5 MHz restriction).

Regards,

David

Hey David,

So you mean Slave clock is already limited to Max. 12.5MHz, we can't achieve above rates by setting LSPCLK, but we are able to lower the limit under the 12.5MHz by changing the LSPCLK. Am i right?

Regards,

Oğuzhan,

hey

Thank you David and Mark for your support.

Best regards.

oğuzhan