• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 84 subscribers
  • Views 3447 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

28335 PWM misfiring for one cycle in phase shift step from zero to any phase.

Robert Vartanian
Prodigy 10 points

Hello,

I`m using 28335 for phase shifted H-bridge dc-dc converter with complimentary configuration in ePWM1 and ePWM2 modules 50% duty cycle, 40kHz, 260ns deadband. While running, when we update the phase shift from zero to anything such as 5deg then 2A and 2B misfire for one cycle (2A remains off and 2B remains on for one full cycle) then start to operate. on the attached scope screen shot channel-1 is 1A and channel-2 is 2B and trigger point is the phase shift step from zero to 5deg. 

any advice?

Robert

  • 0
    TI__Mastermind 24095 points

    Hi Robert,

    One possible case is if the compare event is getting skipped completely because of the phase load.
    For example: Say the compare match value is 10, current counter status is 6 and due to phase load if the counter jumps to say 15 then the compare event is missed. This could result in the waveform above. Please check the timing of phase load and counter status w.r.t compare values.

    -Bharathi.

  • 0 in reply to Subrahmanya
    TI__Genius 10820 points

    Hi Robert,

    I believe I know why you are experiencing this behavior. This is a fixed frequency power topology, so both PWM1 and PWM2 counters are probably operating in the same counting mode and the same period. You are probably using CTR = 0 event of PWM1 to sync PWM2. When the phase value for PWM2 is changed from 0 to a non-zero value, in the very first cycle after this change, PWM2 will not go to CTR = 0 but instead counts from the new phase value. This means that any shadow register loads set to happen at CTR = 0, will not happen. Even worse, the CTR = 0 AQ events will not happen, which is probably why you get this full 100% duty cycle.

    A simple trick I use to overcome this problem is to set 'PWM2 period = PWM1 period - 1'. This will make sure that CTR = 0 event is not skipped. This doesn't really affect the operation frequency either because of the syncing and as long as duty values do not approach 100% (which should not be the case for this topology. Additionally, you can restrict phase value to be always greater than 0 if your system allows it.

    I hope this helps.

    Hrishi

  • 0 in reply to Subrahmanya
    Prodigy 30 points
    Hi Bharathi,
    definitely it is skipping the compare value. I guess the solution Hrishi mentioned avoids it. Thanks anyways.
  • 0 in reply to Hrishi Nene
    Prodigy 30 points
    Hi Hrishi,
    Thanks for the feedback.
    It makes sense if we use 'PWM2 period = PWM1 period - 1'. It seems the problem is solved, but we have another challenging situation which is in driving a dual active bridge system (DAB) using PWM1 &2 for low voltage (LV) side and PWM3&4 for high voltage (HV) side. in Phase Shift mode od DAB we need to have full bridge on both side and shift phase of PWM3 between +90 and -90degree respect to PWM1 !! that also gave us full cycle glitch on PWM3 &4 in 2 events crossing close to 0deg! if we use your suggested method, it might solve the problem.

    Thanks
    Robert
  • 0 in reply to Robert Vartanian67
    TI__Genius 10820 points

    Robert,

    Yes, I think it might be the same root cause for the PWM3 and PWM4 behavior.

    Let me know if the same trick doesn't help.

    BTW nice to see you here on the forums!

    Hrishi

  • 0 in reply to Hrishi Nene
    Prodigy 30 points

    Hi Hrishi,

    I used this solution and for PWM3 and PWM4 and it seems if we use same PRD numbers it does the glitch but I subtracted 1 from the PRD register of each PWM module respect to the one above it and it seems it fixes the problem. There is no problem if we do a phase shift of 1 count per cycle (with a simple ramp function) but with a significant large phase shift (which is not tolerable in hardware) we get a glitch and definitely it skips ZRO.

    Anyway, I`d like to send you my code and get your feedback.

    Regards

    Robert

  • 0 in reply to Robert Vartanian67
    TI__Genius 10820 points

    Hi Robert,

    I am glad that this solution solves the PWM3 - PWM4 issue as well. 

    I think it might be more efficient if you could send me a sketch of expected and desired PWM waveforms instead of the code. It also helps to include the expected PWM time-base counter behavior in the sketch. 

    Hrishi