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Help! I can't get CAN bus working! F28035. Standard addressing. Message arriving at RX pin from host at 250kbps. CANES=0x00100002.

Paul Roberts3
Prodigy 60 points
Other Parts Discussed in Thread: SN65HVD230, CONTROLSUITE

Can someone please point me in the right direction?

1) I'm using CAN transceiver SN65HVD230.

2) The controlSuite example worked, but that only exercises self-test mode.

3) I'm using F28035 on an "Experimenter Board"

4) I'm using CCSv6 with XDS100v1 emulator.

5) Using "Gridconnect" USB/CAN adapter made by Peak.  The PC app is called "PCAN-View."

6) I'm sending Message Id = 0x744 with an 8-byte payload at 250 kbps.

7) I can see the message arriving at the CAN-RX pin with a LeCroy scope with CANbus decoder option.  It shows the "0x744" message packet arriving on the screen along with "ACK Error".  The entire packet width is just under 400 usec.  This is followed by a low-going pulse that comes out of the CAN-TX pin.  This pulse is 4 usec wide.  The PC app sends another packet 100usec after this pulse ends, so there's an attempt being made every 500 usec.

8) I have a breakpoint in the debugger where I wait for (ECanaRegs.CANRMP.all & 0x01uL) to happen, which never happens.

9) Below are the register values I see upon pausing the debugger:

CANES=0x00100002.

CANREC=0x00000081

CANGIF0=0x00000300

SYSCLK=60Mhz

CANBTC=0x00070152

CANGAM=0x9FFFFFFF

CANME=0x00000003

CANMD=0xFFFFFFFD

CANMIM=0x00000003

MBX0_LAM=0x9FFFFFFF

MBX0_MSGCTRL=0x00000008

MBX0_MSGID=0x5D100000

Any ideas or suggestions would be much appreciated.

thanks,

Paul

p.s. Here are some excepts from the code:

#define dSYSCLKOUT_hz     60000000.0

#define dCANQUANTAFREQ_hz 3750000.0
#define CANFREQ_hz 250000
#define CAN_BTCVAL        7

#define CAN_SJW_tq        2         // 1 to 4 quanta
#define CAN_TSEG1_tq      11   // e2e.ti.com/.../248856
#define CAN_TSEG2_tq      3    // e2e.ti.com/.../248856
#define CAN_SJW_reg       (CAN_SJW_tq-1)
#define CAN_TSEG1_reg     (CAN_TSEG1_tq-1)
#define CAN_TSEG2_reg     (CAN_TSEG2_tq-1)

void InitCANConnectionTest(void)
 {
  struct ECAN_REGS ECanaShadow;

     MessageReceivedCount = 0;
  InitECanaGpio();
  InitECana(); // Initialize eCAN-A module

     EALLOW;
      ECanaRegs.CANME.all = 0x00000000;
  EDIS;
  ///////////////////////////////////////////

 /* Configure bit timing parameters for eCANA*/

     EALLOW;
     ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
     ECanaShadow.CANMC.bit.SUSP = 1 ;            // FREE mode - Run CAN peripheral in the debugger.
     ECanaShadow.CANMC.bit.DBO = 0;            //  Little Endian => BYTE0 is LS.
     ECanaShadow.CANMC.bit.SCB = 0;            //  SCC compatibility bit
     ECanaShadow.CANMC.bit.CDR = 0;     //  "Change Data Request" set to 1 to change TX mailbox data
     ECanaShadow.CANMC.bit.ABO = 1; //  "Auto Bus On" after 128*11 recessive bits have been montiored.

     ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
  EDIS;

  ///////////////////////////////////////////

  CanaEnableConfigChangeSysCtrlRegs(); // CCR=1, CCE=1.

  ///////////////////////////////////////////

     /* The following block is only for 60 MHz SYSCLKOUT. (30 MHz CAN module clock Bit rate = 1 Mbps
        See Note at end of file. */

      EALLOW;     // EALLOW enables access to protected bits
  ECanaShadow.CANBTC.all = 0;      /* Clear shadow reg */
  ECanaShadow.CANBTC.bit.BRPREG = CAN_BTCVAL;    /* Set parameters */
  ECanaShadow.CANBTC.bit.SJWREG = CAN_SJW_reg ;
  ECanaShadow.CANBTC.bit.TSEG1REG = CAN_TSEG1_reg;
  ECanaShadow.CANBTC.bit.TSEG2REG = CAN_TSEG2_reg;
   ECanaShadow.CANBTC.bit.SAM = 0;
  ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; /* Write to actual ECAN reg */
  EDIS;

     EALLOW;     // EALLOW enables access to protected bits
     ECanaRegs.CANGIM.all = 0;         // applies to MB15:6
  EDIS;

  ///////////////////////////////////////////

  CanaDisableConfigChangeSysCtrlRegs();  // CCR=0, CCE=0.

  ///////////////////////////////////////////

     EALLOW;     // EALLOW enables access to protected bits
     // Configure Mailboxes 1 as Tx, 0,2-31 as Rx
     // Since this write is to the entire register (instead of a bit
     // field) a shadow register is not required.
     ECanaRegs.CANMD.all = 0xfffffffd;
  EDIS;

  ///////////////////////////////////////////
  
     EALLOW;     // EALLOW enables access to protected bits
     ECanaRegs.CANGAM.all = 0x9fffffff;
  EDIS;

     EALLOW;     // EALLOW enables access to protected bits
     ECanaMboxes.MBOX0.MSGID.all = 0;
     //ECanaMboxes.MBOX0.MSGID.bit.AME = 0; // Us an acceptance mask.
     ECanaMboxes.MBOX0.MSGID.bit.AME = 1; // Use an acceptance mask.
     ECanaMboxes.MBOX0.MSGID.bit.IDE = 0; // Received message has STANDARD ID.
     ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = 0x744uL;
  EDIS;

  CanaEnableConfigChangeSysCtrlRegs(); // CCR=1, CCE=1.

     EALLOW;     // EALLOW enables access to protected bits
  ECanaLAMRegs.LAM0.all = 0x1fffffffuL; // Accept anything (Throw out a big net).
         ECanaLAMRegs.LAM0.bit.LAMI = 1; // USE THE ACCEPTANCE MASK.
  EDIS;

  CanaDisableConfigChangeSysCtrlRegs(); // CCR=0, CCE=0.

     EALLOW;     // EALLOW enables access to protected bits
     ECanaMboxes.MBOX0.MSGCTRL.all = 0;
     ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;  // Number of bytes to receive.
     ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0;  // No remote frame is requested.
      EDIS;

  //////////////////////////////////////////////////////////////////////////////////////////

     EALLOW;     // EALLOW enables access to protected bits
     ECanaMboxes.MBOX1.MSGID.all = 0;
     ECanaMboxes.MBOX1.MSGID.bit.AAM = 0; // No acceptance mask.
     ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = 0x0ffuL;
  EDIS;

  CanaEnableConfigChangeSysCtrlRegs(); // CCR=1, CCE=1.

     EALLOW;     // EALLOW enables access to protected bits
     ECanaLAMRegs.LAM1.all = 0x00000000;
     ECanaLAMRegs.LAM1.bit.LAM_H = 0x0000; //28:16 => This field is 13 bite wide.
     ECanaLAMRegs.LAM1.bit.LAM_L = 0x0000; //15:0
     ECanaLAMRegs.LAM1.bit.LAMI = 1; // USE THE ACCEPTANCE MASK.
  EDIS;

  CanaDisableConfigChangeSysCtrlRegs(); // CCR=0, CCE=0.

     EALLOW;     // EALLOW enables access to protected bits
     ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
     ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;  // Number of bytes to transmit.
     ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0;  // No remote frame is requested.
     ECanaMboxes.MBOX1.MSGCTRL.bit.TPL = CANMSGPRIORITY_STANDARD; // Applies to TX
  EDIS;

     EALLOW;     // EALLOW enables access to protected bits
     ECanaMboxes.MBOX1.MDL.all = 0x5f427664;
     ECanaMboxes.MBOX1.MDH.all = 0x41636b56; //
  EDIS;

  ///////////////////////////////////////////

  // Mailbox Interrupt Mask Register (CANMIM)

     EALLOW;     // EALLOW enables access to protected bits
     ECanaRegs.CANMIM.all = 0x00000003;
  EDIS;

     EALLOW;     // EALLOW enables access to protected bits
     ECanaRegs.CANME.all = 0x00000003;
  EDIS;
 }

void CANConnectionTest_Service(void)
 {
  static enum
  {
   CANLOOPBACK_AWAIT_RECEIPT,
   CANLOOPBACK_TRANSMIT,
   CANLOOPBACK_AWAIT_XMIT_ALL,
   CANLOOPBACK_AWAIT_XMIT_ACKS,
   NUM_CANLOOPBACK_STATES
  }state = CANLOOPBACK_AWAIT_RECEIPT;
  //}state = CANLOOPBACK_TRANSMIT;

  switch(state)
  {
   case CANLOOPBACK_AWAIT_RECEIPT:
   {
    CANPayload_t payload;

    /* Received-Message-Pending Register (CANRMP)
     *  RMP[31:0] Received-message-pending bits.
     * 1 = If mailbox n contains a received message, bit RMP[n] of this register
     * is set.
     * 0 = The mailbox does not contain a message.
     */
          if((ECanaRegs.CANRMP.all & 0x00000001uL) !=  0x00000001uL)
     break;
          ECanaRegs.CANRMP.all = 0x00000001uL;  // Reset the bits

       MessageReceivedCount++;

/*  NOTE: THIS IS WHERE I PUT MY BREAKPOINT. */

/* THE CODE NEVER ARRIVES HERE . */

       //Read from Receive mailboxes and begin checking for data */
    mailbox_read(0, &payload, (uint32_t *)0);

    if(!strncmp((char *)payload.data, "#DRS-CCI", MAX_STD_CAN_PAYLOAD_LEN))
    {
     // It matches.
     state = CANLOOPBACK_TRANSMIT;
    }
    break;
   }

   case CANLOOPBACK_TRANSMIT:
    /* Transmission-Request Set Register (CANTRS)
     * 1 = Setting TRSn transmits the message in that mailbox. Several bits can
     * be set simultaneously with all messages transmitted in turn.
     */
       // Begin transmitting
          ECanaRegs.CANTRS.all = 0x00000002uL;  // Set TRS to transmit contents of mailbox #1
    state = CANLOOPBACK_AWAIT_XMIT_ALL;
    break;

    case CANLOOPBACK_AWAIT_XMIT_ALL:
    // Did the message go out?
          if((ECanaRegs.CANTRS.all & 0x00000002uL) !=  0x00000000uL)
     break;
    state = CANLOOPBACK_AWAIT_XMIT_ACKS;
    break;

   case CANLOOPBACK_AWAIT_XMIT_ACKS:
    /* Transmission-Acknowledge Register (CANTA)
     * TA[31:0] Transmit-acknowledge bits.
     * 1 = If the message of mailbox n is sent successfully, the bit n of this
     * register is set.
     * 0 = The message is not sent.
     */
#if 1
          if(ECanaRegs.CANTA.all != 0x00000002 )
     break;
#endif
       ECanaRegs.CANTA.all = 0x00000002;   // Clear TA1
   default:
    //state = CANLOOPBACK_AWAIT_RECEIPT;
    state = CANLOOPBACK_TRANSMIT;
    break;
  }
 }

void InitECana(void)        // Initialize eCAN-A module
{

/* Create a shadow register structure for the CAN control registers. This is
 needed, since only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents or return
 false data. */

struct ECAN_REGS ECanaShadow;

    EALLOW;     // EALLOW enables access to protected bits


/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
    ECanaRegs.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANRIOC.bit.RXFUNC = 1;

/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
                                    // HECC mode also enables time-stamping feature
/* Disable all Mailboxes  */
    ECanaRegs.CANME.all = 0;        // Required before writing the MSGIDs

 EDIS;

 CanaDisableSCCCompatibleMode();

    EALLOW;     // EALLOW enables access to protected bits
/* Initialize all bits of 'Message Control Register' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero

    ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
 EDIS;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
//  as a matter of precaution.

    EALLOW;     // EALLOW enables access to protected bits
    ECanaRegs.CANTA.all = 0xFFFFFFFF;   /* Clear all TAn bits */
    ECanaRegs.CANRMP.all = 0xFFFFFFFF;  /* Clear all RMPn bits */
    ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
    ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
 EDIS;

 CanaEnableConfigChangeSysCtrlRegs();

/* Configure bit timing parameters for eCANA*/

    EALLOW;     // EALLOW enables access to protected bits
    ECanaShadow.CANBTC.all = 0;
    /* The following block is only for 60 MHz SYSCLKOUT. (30 MHz CAN module clock Bit rate = 1 Mbps
       See Note at end of file. */

    ECanaShadow.CANBTC.bit.BRPREG = 2;
    ECanaShadow.CANBTC.bit.TSEG2REG = 1;
    ECanaShadow.CANBTC.bit.TSEG1REG = 6;
    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
 EDIS;

 CanaDisableConfigChangeSysCtrlRegs();

/* Disable all Mailboxes  */
    EALLOW;     // EALLOW enables access to protected bits
    ECanaRegs.CANME.all = 0;        // Required before writing the MSGIDs
    EDIS;

    EALLOW;     // EALLOW enables access to protected bits
 SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1;  // Added 3/28/2016 PJR.  Start the CAN clock!
    EDIS;
}

static void mailbox_read(int16 mailbox_num, CANPayload_t *payload, uint32_t *pMessageId)
 {
    volatile struct MBOX *Mailbox;

    Mailbox = &ECanaMboxes.MBOX0 + mailbox_num;

    if(payload)
    {
     *((uint32_t *)&payload[0]) = Mailbox->MDH.all;
     *((uint32_t *)&payload[4]) = Mailbox->MDL.all;
    }
    if(pMessageId)
    {
   *pMessageId = Mailbox->MSGID.all;
    }
 } // MSGID of a rcv MBX is transmitted as the MDL data.

void CanaEnableConfigChangeSysCtrlRegs(void)
{
 struct ECAN_REGS ECanaShadow;

    EALLOW;     // EALLOW enables access to protected bits
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    // Wait until the CPU has been granted permission to change the configuration registers
    do
    {
      ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 1 );       // Wait for CCE bit to be set..
 EDIS;
}

void CanaDisableConfigChangeSysCtrlRegs(void)
{
 struct ECAN_REGS ECanaShadow;

    EALLOW;     // EALLOW enables access to protected bits
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    // Wait until the CPU no longer has permission to change the configuration registers
    do
    {
      ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 );       // Wait for CCE bit to be  cleared..
 EDIS;
}

void CanaEnableSCCCompatibleMode(void)
{
 struct ECAN_REGS ECanaShadow;

    EALLOW;     // EALLOW enables access to protected bits
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.SCB = 1;
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
 EDIS;
}

void CanaDisableSCCCompatibleMode(void)
{
 struct ECAN_REGS ECanaShadow;

    EALLOW;     // EALLOW enables access to protected bits
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.SCB = 0;
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
 EDIS;
}

  • 0
    TI__Guru* 95315 points

    Paul,

      It would be easier if you let the 28035 transmit and the PEAK CAN dongle receive first. Transmit problems are relatively easy to debug. Let the 28035 transmit without the CAN dongle connected. There will be an ACK error and the transmission would be repeated forever. That is OK. Just capture this waveform on the scope and ensure that the width of the bit (bit-rate) is 4 uS. Now, you have verified the bit-timing parameters are all OK. Then connect the CAN dongle and make sure the messages are received correctly. If you reach this stage, it means there are no hardware issues. Now try reception on the 28035. Try this without Acceptance Mask Filtering first. i.e. the transmitted MSGID and the MSGID of the Receive MBX are exactly identical and no mask bits are used. If you reach this point, then go for filtering. I also notice that CANREC is not 0 and CANES indicates Stuff-Error.

    Try my suggestions in the sequence outlined..