Unwaited interrupt

yeah, this seems weird. Is PIEIER1 enabled at any point in your code and is ADCA1 set-up at any point in your code?
does the problem happen at the same point always? Can you check your code if you are configuring PIE twice? what happens if you do not enable INT4?

PIE VECT shows 0xD40 (INT1)
PIE ACK for INT1 is set
PIEIFR and PIEIER for INT4 is set.


Best Regards
Santosh Athuru

Hello

Sorry for the late, I'm was in vacation.

I used the INT4 for XINT1 to get an external signal interrupt from an EtherCAT controller.

My Init code is like following:

PieVectTable.XINT1_INT = &EscIsr;

PieCtrlRegs.PIEIER1.bit.INTx3 = 1; // Enable ADCC1INT in PIE group 1
PieCtrlRegs.PIEIER1.bit.INTx4 = 1; // Enable PIE Group 1 INT4 (for XINT1)

IER |= M_INT1; // Enable group 1 interrupts
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
EDIS;

// GPIO69 are inputs
EALLOW;
GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 0; // GPIO
GpioCtrlRegs.GPCDIR.bit.GPIO69 = 0; // input
GpioCtrlRegs.GPCQSEL1.bit.GPIO69 = 0; // XINT1 Synch to SYSCLKOUT only
EDIS;

// GPIO69 is XINT1
GPIO_SetupXINT1Gpio(69);

// Configure XINT1
XintRegs.XINT1CR.bit.POLARITY = 0; // Falling edge interrupt

// Enable XINT1
XintRegs.XINT1CR.bit.ENABLE = 1; // Enable XINT1

 

Then I use a generic stack which allow to dialog with an external EtherCAT controller (Beckhoff ET1100).

This stack is called SSC for Slave Stack Code and the link with extarnal controller is via the SPI.

To work correctly, we need to disable sometime the external interrupt from this controller (during SPI Read/Write access)

Then the following macro is used:

#define DISABLE_ESC_INT() (PieCtrlRegs.PIEIER1.bit.INTx4 = 0)
#define ENABLE_ESC_INT() (PieCtrlRegs.PIEIER1.bit.INTx4 = 1)

With this code, I have the trouble explain on my first post.

Then I try two things:

1) May be the access to PieCtrlRegs.PIEIER1.bit.INTx4 is composed by many assembler instruction , then maybe we are interrupted between them and cause problem.

So I try following:

#define DISABLE_ESC_INT() DINT;(PieCtrlRegs.PIEIER1.bit.INTx4 = 0);EINT;
#define ENABLE_ESC_INT() DINT;(PieCtrlRegs.PIEIER1.bit.INTx4 = 1);EINT;

But problem still present.

 

2) So I try following:

#define DISABLE_ESC_INT()
#define ENABLE_ESC_INT()

This is radical and can cause problem for my Read/write on SPI access!

So with this, ADCA1_ISR interruption not occurs, problem dessapears!.

 

3) I had also tested the following solution which work:

#define DISABLE_ESC_INT() (XintRegs.XINT1CR.bit.ENABLE = 0)
#define ENABLE_ESC_INT() (XintRegs.XINT1CR.bit.ENABLE = 1)

I'm not able to know which is the beter solution between  Enable/Disable Xint or Pier Xint4? (If we forget the problem with the last solution...)

 

An idea..?