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PWM Functionality

ramakrishna dutt
Intellectual 760 points
Other Parts Discussed in Thread: CONTROLSUITE

hi,

I am using EPWM1,2,3 in my code.

For EPWM1 I am using the lines as:

void InitEPwm1()
{
// EPWM Module 1 config
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Period = TBCLK counts
EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Symmetrical mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM1A
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;

EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // set actions for EPWM1A

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

// Set Compare values
EPwm1Regs.CMPA.half.CMPA = 0; // Set compare A value 300, 124
EPwm1Regs.CMPB = 544; // Set Compare B value

EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBFED = 9; // FED = 20 TBCLKs 6-->100ns; 9-->150ns
EPwm1Regs.DBRED = 9; // RED = 20 TBCLKs

}


void InitEPwm2()
{
// EPWM Module 2 config
EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Period = TBCLK counts
EPwm2Regs.TBPHS.half.TBPHS = 272; // Phase = (272/544)*360 = 180 deg
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Symmetrical mode
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM2A
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR;

EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;
EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // set actions for EPWM2B

// Set Compare values
EPwm2Regs.CMPA.half.CMPA = 0; // Set compare A value
EPwm2Regs.CMPB = 544; // Set Compare B value

EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi Complementary
EPwm2Regs.DBFED = 9; // FED = 20 TBCLKs 6-->100ns; 9-->150ns
EPwm2Regs.DBRED = 9; // RED = 20 TBCLKs

EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

}


void InitEPwm3()
{
// EPWM Module 3 config
EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Period = TBCLK counts
EPwm3Regs.TBPHS.half.TBPHS = 0;
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Symmetrical mode
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1A
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;

EPwm3Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // set actions for EPWM1A
EPwm3Regs.AQCTLB.bit.CAU = AQ_SET;

// Set Compare values
EPwm3Regs.CMPA.half.CMPA = 3000; // Set compare A value
EPwm3Regs.CMPB =1500; // Set Compare B value

EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi Complementary
EPwm3Regs.DBFED = 9; // FED = 30 TBCLKs 6-->100ns; 9-->150ns
EPwm3Regs.DBRED = 9; // RED = 30 TBCLKs

EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;

}

Now my problem is if I am using lines in EPWM3 as the following:

EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

I am not getting PWM Output.

May I know the reason.

Please.

  • 0
    Intellectual 760 points
    All the concerned Interrupt lines are written.
    I am using EPMW1, 2 As free running PWM'S.

    I am using EPWM3 to trigger ADC.
  • 0 in reply to ramakrishna dutt
    TI__Mastermind 24095 points
    Hi,


    TBCLKSYNC can be written one in the end when all PWMs are initialized. It will enable the operation of all PWMs simultaneously.
    No need to have it multiple times in every PWM config.
    EALLOW;
    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    EDIS;

    Also, Is PWM1 working? Do you get any outputs there?
    What about PWM2 or is the Problem with 3 only?

    There are several examples on controlSuite for these basic configurations. You can try the example first.

    -Bharathi.