running the scia and scib simultaneously

Other Parts Discussed in Thread: TMS320F28377D

#include "F28x_Project.h"     // Device Headerfile and Examples Include File
//#include "stdio.h"


#define CPU_FREQ    200E6
#define LSPCLK_FREQ CPU_FREQ/4
#define dx_baud 1

interrupt void sciaRxFifoIsr(void);
interrupt void scibRxFifoIsr(void);

void scia_fifo_init(void);
void scib_fifo_init(void);


Uint16 rdataA[8];    // Received data for SCI-A
Uint16 rdataB[8];    // Received data for SCI-A

Uint16 rxcount;
Uint16 rxcount2;

Uint32 loopcount;


Uint16 countm;

void main(void)
{

   rxcount = 0;
   rxcount2 = 0;
   loopcount = 0;


   InitSysCtrl();

   EALLOW;											// PWM 모듈에 공급되는 시스템 클럭 분주
   ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;		// 0: 1분주, 1: 1/2분주
   EDIS;

   InitGpio();



   EALLOW;
   // GPIO FOR A SCI
   GPIO_SetupPinMux(28, GPIO_MUX_CPU1, 1);
   GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_PUSHPULL);
   GPIO_SetupPinMux(29, GPIO_MUX_CPU1, 1);
   GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);

   GPIO_SetupPinMux(55, GPIO_MUX_CPU1, 1);
   GPIO_SetupPinOptions(55, GPIO_INPUT, GPIO_PUSHPULL);
   GPIO_SetupPinMux(54, GPIO_MUX_CPU1, 1);
   GPIO_SetupPinOptions(54, GPIO_OUTPUT, GPIO_ASYNC);


   EDIS;



   DINT;



   InitPieCtrl();

   IER = 0x0000;
   IFR = 0x0000;
   InitPieVectTable();

   EALLOW;  // This is needed to write to EALLOW protected registers
   PieVectTable.SCIA_RX_INT = &sciaRxFifoIsr;
   PieVectTable.SCIB_RX_INT = &scibRxFifoIsr;

 // Step 4. Initialize the Device Peripherals:
   scia_fifo_init();  // Init SCI-A
   scib_fifo_init();  // Init SCI-B



// Step 5. User specific code, enable interrupts:

// Init send data.  After each transmission this data
// will be updated for the next transmission

// Enable interrupts required for this example
   PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block
   PieCtrlRegs.PIEIER9.bit.INTx1=1;     // PIE Group 9, INT1
   PieCtrlRegs.PIEIER9.bit.INTx2=0;     // PIE Group 9, INT2

   PieCtrlRegs.PIEIER9.bit.INTx3=1;     // PIE Group 9, INT1
   PieCtrlRegs.PIEIER9.bit.INTx4=0;     // PIE Group 9, INT2


   IER = 0x100;   // Enable CPU INT

   IER |= M_INT9;




   EINT;   // Enable Global interrupt INTM
   ERTM;   // Enable Global realtime interrupt DBGM

 

// Step 6. IDLE loop. Just sit and loop forever (optional):
    for(;;)
    	{



    		ScibRegs.SCITXBUF.all= 0x01;

    		DELAY_US(10);

    		loopcount++;


    	}

}

interrupt void sciaRxFifoIsr(void)
{
    Uint16 i;

    rxcount++;
    for(i=0;i<8;i++)
    {
       rdataA[i]=SciaRegs.SCIRXBUF.all;  // Read data
    }

    SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1;   // Clear Overflow flag
    SciaRegs.SCIFFRX.bit.RXFFINTCLR=1;   // Clear Interrupt flag

    PieCtrlRegs.PIEACK.all|=0x100;       // Issue PIE ack
}

interrupt void scibRxFifoIsr(void)
{
    Uint16 i;

    rxcount2++;
    for(i=0;i<8;i++)
    {
       rdataB[i]=ScibRegs.SCIRXBUF.all;  // Read data
    }

    ScibRegs.SCIFFRX.bit.RXFFOVRCLR=1;   // Clear Overflow flag
    ScibRegs.SCIFFRX.bit.RXFFINTCLR=1;   // Clear Interrupt flag

    PieCtrlRegs.PIEACK.all|=0x100;       // Issue PIE ack
}



void scia_fifo_init()
{

 
   SciaRegs.SCICCR.all =0x0007;   
	                             
	                             
   SciaRegs.SCICTL1.all =0x0003;  
	                               

   SciaRegs.SCICTL1.bit.SWRESET = 0;		

   SciaRegs.SCICCR.bit.SCICHAR = 7;		
   SciaRegs.SCICCR.bit.LOOPBKENA = 0;		

   SciaRegs.SCICTL1.all = 0x0003;
   SciaRegs.SCICTL1.bit.RXENA = 1;			
   SciaRegs.SCICTL1.bit.TXENA = 1;			
   SciaRegs.SCICTL2.bit.TXINTENA = 0;		
   SciaRegs.SCICTL2.bit.RXBKINTENA = 1;	    

   SciaRegs.SCIHBAUD.all    = 0x0002;  // 9600 baud @LSPCLK = 50MHz (200 MHz SYSCLK).
   SciaRegs.SCILBAUD.all    = 0x008B;
  

   SciaRegs.SCICTL1.bit.SWRESET = 1;		

   PieCtrlRegs.PIEIER9.bit.INTx2 = 0;		
   PieCtrlRegs.PIEIER9.bit.INTx1 = 1;		

}


void scib_fifo_init()
{

 
   ScibRegs.SCICCR.all =0x0007;   // 1 stop bit,  No loopback
	                              // No parity,8 char bits,
	                              // async mode, idle-line protocol
   ScibRegs.SCICTL1.all =0x0003;  // enable TX, RX, internal SCICLK,
	                               // Disable RX ERR, SLEEP, TXWAKE

   ScibRegs.SCICTL1.bit.SWRESET = 0;		

   ScibRegs.SCICCR.bit.SCICHAR = 7;		
   ScibRegs.SCICCR.bit.LOOPBKENA = 0;		

   ScibRegs.SCICTL1.all = 0x0003;
   ScibRegs.SCICTL1.bit.RXENA = 1;			
   ScibRegs.SCICTL1.bit.TXENA = 1;			
   ScibRegs.SCICTL2.bit.TXINTENA = 0;		
   ScibRegs.SCICTL2.bit.RXBKINTENA = 1;	    

   ScibRegs.SCIHBAUD.all    = 0x0002;  // 9600 baud @LSPCLK = 50MHz (200 MHz SYSCLK).
   ScibRegs.SCILBAUD.all    = 0x008B;
  
   ScibRegs.SCICTL1.bit.SWRESET = 1;		

   PieCtrlRegs.PIEIER9.bit.INTx4 = 0;		
   PieCtrlRegs.PIEIER9.bit.INTx3 = 1;		

}

I want to run scia and scib.

scia is working on the code above, but i can not run the scib.

could you tell me what is wrong in the code?

thanks.