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CLA issuing software task interrupt



In the documentation it states: (with regard to the CLA)

Software Trigger

Tasks can also be started by the main CPU software writing to the MIFRC register or by the IACK

instruction. Using the IACK instruction is more efficient because it does not require you to issue an

EALLOW to set MIFR bits. Set the MCTL[IACKE] bit to enable the IACK feature. Each bit in the

operand of the IACK instruction corresponds to a task. For example IACK #0x0001 will set bit 0 in the

MIFR register to start task 1. Likewise IACK #0x0003 will set bits 0 and 1 in the MIFR register to start

task 1 and task 2.

The question is:  If I have one CLA servicing 2 ADCs, the way I see it the best I can do is have each ADC generate it's own interrupt, which results in two tasks in the CLA.  If the data I am reading from both ADCs is actually from an array, so I wish to process them together, I would have to do something like having task 1 copy the ADC registers, then check a self created flag if task 2 has occurred.  If not, then return.

In task 2 I would copy it's ADC result registers to a common location (creating an array of ADC1 and ADC2 result registers... so if I'm reading 6 results on each ADC this creates 12 ADC result registers (Vector of data).  Now in task 2 I can check the flag if task 1 is complete, in this example it is, so then I can call my processing to process the data, and clear the flags for the next iteration.   Similarily, if task 2 happened to occur furst, then task 1 is checking the flags and it would call the processing if task 2 occurred first.

Now in the interest of having only one interrupt to the CPU, one idea would be to have task 1 or 2 of the CLA initiate a software TASK interrupt which would then process the combined vector of data, so task 1 and 2 essentially just do a 6 memory moves and test flags and return without generating a CPU inttrupt... but if the alternate task is complete, then either task will initiate the software task interrupt, which will process the data, and it will generate a CPU interrupt.  In this way the CPU has no knowledge of this 'combination' of tasks occurring at the CLA.

The idea is, if later I put all 4 or 3 ADCs to be processed by the CLA I have isolated that from the CPU, so it only knows about servicing a 'complete' interrupt.

So the question is:

1.  Can the CLA initiate it's own software inttrupt?  I assume with the MEALLOW and MEDIS?  but baed on the above documentation it only talks about it in the context of doing this from the main CPU, not from the CLA.  I just want ot verify this is an allowed process?  will it cause any issues?

2.  Is there any other way to combine ADC End of Conversion interrupts, so that no EOC is created unitl two or 3 or 4 ADCs are complete?  So I can collect the results from all read values from any number of ADCs in one CLA task?

Thanks.

  • Rob Barton said:
    1.  Can the CLA initiate it's own software inttrupt?  I assume with the MEALLOW and MEDIS?  but baed on the above documentation it only talks about it in the context of doing this from the main CPU, not from the CLA.  I just want ot verify this is an allowed process?  will it cause any issues?

    You cant have a CLA task trigger another. What you could do is trigger an interrupt at the main CPU mid-task (using the Cla1SoftIntRegs - this is available only on type 1 CLAs, on the 2837xD/S) and then have the CPU ISR trigger another task. The CLA cannot write to its own configuration registers

    Rob Barton said:
    2.  Is there any other way to combine ADC End of Conversion interrupts, so that no EOC is created unitl two or 3 or 4 ADCs are complete?  So I can collect the results from all read values from any number of ADCs in one CLA task?

    Well if you have 4 adcs sampling in sequence you could just have the last ADC trigger the task then read all 4 adc result registers. Did i misunderstand your question?

  • Thanks. We are using the 28375D.

    With regard to Q2:
    Using figure 9-1 of spruHM8e

    It is my understanding that ADC-A, ADC-B, ADC-C, and ADC-D each have to have their own interrupts listed in table 5-1 (CLA module) as ADCAINT1,2,3,4 and ADCBINT1,2,3,4 etc. Ideally I would like to see some form of AND gate say:

    NEWINTERRUPT = ADCAINT1 & ADCBINT1 & ADCCINT1 & ADCDINT1 (assuming I setup the individual ADC in high priority mode, then I can have each one service the 6 SOCs in order and only generate one EOC on the completion of the final one....)

    So within an ADC I can control the order and force the interrupt from say ADC-A or ADC-B to only generate when its complete... but between the 4 ADC's how can I accomplish the same thing?

    I am sampling an array of 24 elements, ideally I want to sample them simultaneously, so I've set all ADCs to trigger off of a CPU clock, and we will just accept that each of the 4 ADCs is sampling 6 sequentially, but Even if we could trigger one ADC-B from ADC-A, I would not desire to sample all 24 sequentially if at all possible. It's best to have 4 sets of 6 sampling as 'close' to simultaneously as possible.

    I can solve this multiple ways, but I was trying to 'combine' 2 ADCs on each CLA to maximize processing time, and collect 12 results on each, and then only have one interrupt to the CPU, ideally. I could just have 2 Tasks on the CLA, one for each ADC- do the same kind of flag checking so only the later of the two will actually process the data, but then the CPU must monitor 2 CLA interrupts since it doesn't know which one will fire to indicate that the data is processed, so it will work, but i's just tieing up an additional interrupt and makes it a bit more confusing ... it would be nice to combine this at the CLA if it's possible.

    Any other suggestions as to how to combine 2 or more ADCs results at the CLA would be appreciated, in a way that will only generate one interrupt to the CPU, ideally.

    Thanks.
  • I just had an Idea.

    Would this work:

    In the case where we are talking about just one CLA for the moment, and in the case where we are just talking about 2 ADC-A and say ADC-B.

    If I create two tasks, but I point the task interrupt table for the two tasks to the same function, then I set both ADC-A and ADC-B appropriately, say we set ADC-A to generate ADCINT1 and set ADC-B to generate ADCINT1 after EOC5 (6th AD input converted)

    This means as one of the two ADC-A or B finishes, it would generate an interrupt...

    Now if I configure the CLA task 1 to accept an interrupt from ADCAINT1 and task 2 to accept an interrupt from ADCBINT1 then task 1 or 2 will fire, but if I point them both to the SAME function, then the same function will run both times. If I put a flag in the function so that the first time it is called it does nothing and returns immediately, and the second time it is called it reads all the 12 ADC result registers and processes them. When its done processing here is the question:

    Can I have any task set a SOFTWARE interrupt as if from any task? So since task 1 or 2 might have fired in either order, but I'm sending it to the same interrupt handler, if I just had ONE piece of code that sets the software (SOFTINTFRC) register... does it know which 'task' it is? It states that if we don't enable the software interrupt (SOFTINTEN) then each task will automatically initiate a CLA to CPU interrupt of the appropriate task... but if I enabled 2 tasks (the ones being used) as software interrupt enabled... could I manually set just say TASK 1 Software interrupt? so the CPU only has to monitor the task 1 CLA interrupt line even though I might be setting the software interrupt from task 1 or task 2 (since both task 1 & 2 could be the one initiated by the associated ADC)

    Would there be any conflict with doing that?

    Thanks.
  • I guess I need to ask this as well:

    If I can't set a software interrupt for a given task, from any task... if I am constrained to only setting the software CLA to CPU interrupt from the task I'm in, then I could have the CPU and set its interrupt handler table to point to the same handler function for all CLA tasks, so it will respond to any one of them the same, regardless of whichever is the one to initiate the interrupt.

    However I need to be sure that if I enable software interrupts generation in the CLA, that if I don't set a software interrupt in a task, the task will finish quietly without telling anyone... so the main CPU wouldn't know that say task 1 completes until task 2 completes and sends a software generated interrupt... relying on some common memory (counter/flag) that both task 1 & 2 can access in the CLA as a means of communication between tasks in the CLA so I can have one task communicate to the other task it's been completed, but not bother the CPU until the 2nd task in the CLA is complete... this of course could be extended to all 4 ADCs... or 4 tasks in the CLA, where I only fire one software interrupt after the Nth (4 in this example) is run in the CLA...

    So the question here is, by enabling software interrupts for a given CLA task, but not initiating a software interrupt from that task, would that CLA remain silent and complete without informing anyone (other than through a memory/flag/counter setup by me in the CLA that all tasks can access?
  • Rob,
    PIE IFR bits for the CLA interrupts will be set that can looked up by the CPU code as well, in case the PIE interrupts for CLA are not enabled.

    Best Regards
    Santosh Athuru