TMS320F2806x - SCI issues

Any insights?

Jameel,

Have you tried working with the examples in controlSUITE? I would suggest incrementally modifying them to include both SCI ports. This may shed some light on what is incorrect in your code.

Regards
Lori

Jameel,

1) What exactly are you trying to achieve?  Please explain clearly.  

2) Do you want to use FIFO enhancements or not?    

a) In your code, you disabled FIFO enhancements for SCI-A and SCI-B but you enabled FIFO receive interrupt for both SCI-A and SCI-B.  FIFO receive interrupt would not work without enabling FIFO enhancements.

b) Note that TXFFST bits are status flags and are read-only.  If you want to use TX FIFO, then you can configure the TXFFIL if you wish to generate an interrupt based on the number of bytes available in TX FIFO.

3) Do you want to use interrupt for transmitting?  

a) In your code, you enabled TX non-FIFO interrupt but you did not enable TX interrupt at PIE level.  

b) In your code, you enabled TX non-FIFO interrupt but you are also polling for the TXEMPTY bit. Why are you doing both?  If you enable TX interrupt in SCI module and at PIE level, then you don't have to poll again.

4) I don't see any code for SCI receiving but you enabled RX interrupt in SCI and at PIE level.  Are you polling for receive or do you have SCI RX ISRs?  If polling, make sure to use the correct flag fields for FIFO vs Non-FIFO.  You can refer to "Table 13-6. SCI Interrupt Flags" in TRM @ http://www.ti.com/lit/ug/spruh18f/spruh18f.pdf    

5) Note that you need to enable clock to a module before configuring it's registers.  You are enabling the clock to the module in the middle of configuration.    

6) Try SCI echoback example (C:\ti\controlSUITE\device_support\f2806x\vx\F2806x_examples_ccsv5\sci_echoback).  Then modify it for SCI-B.  Then integrate both SCI-A and SCI-B.

Thanks and regards,

Vamsi

Thanks Sal, Lori and Vamsi.

Based on your feedback, I will use the controlsuite code and incrementally change code to add both SCI ports 

@Vamsi - Thanks for the detailed analysis. I'm not planning to use FIFO enhancement. I will make changes as you suggested. Thanks again.

Vamsi,

Current Status - SCIA TX and RX works, SCIB only TX is working(i.e. SCIB RX not working).

Gibberish on SCIB was on account of wrong BUAD rate

I have made code changes per your suggestion(Please let me know if I misunderstood you). Please see code below.

Please see answers to your questions below.

Regards,

Jameel

Vamsi Gudivada said:

Jameel,

1) What exactly are you trying to achieve?  Please explain clearly.  

 >> SCIA and SCIB with RX interrupts. No TX Interrupt.

2) Do you want to use FIFO enhancements or not?   >> No

a) In your code, you disabled FIFO enhancements for SCI-A and SCI-B but you enabled FIFO receive interrupt for both SCI-A and SCI-B.  FIFO receive interrupt would not work without enabling FIFO enhancements.

>> I have disabled FIFO. See code below

b) Note that TXFFST bits are status flags and are read-only.  If you want to use TX FIFO, then you can configure the TXFFIL if you wish to generate an interrupt based on the number of bytes available in TX FIFO.

>> Commented out.

3) Do you want to use interrupt for transmitting?  

a) In your code, you enabled TX non-FIFO interrupt but you did not enable TX interrupt at PIE level.  

>> ScibRegs.SCIFFTX.bit.TXFIFOXRESET

b) In your code, you enabled TX non-FIFO interrupt but you are also polling for the TXEMPTY bit. Why are you doing both?  If you enable TX interrupt in SCI module and at PIE level, then you don't have to poll again.

4) I don't see any code for SCI receiving but you enabled RX interrupt in SCI and at PIE level.  Are you polling for receive or do you have SCI RX ISRs?  If polling, make sure to use the correct flag fields for FIFO vs Non-FIFO.  You can refer to "Table 13-6. SCI Interrupt Flags" in TRM @ http://www.ti.com/lit/ug/spruh18f/spruh18f.pdf    

>> Interrupt for RX. Added section of code below.

5) Note that you need to enable clock to a module before configuring it's registers.  You are enabling the clock to the module in the middle of configuration.    

Moved it.

6) Try SCI echoback example (C:\ti\controlSUITE\device_support\f2806x\vx\F2806x_examples_ccsv5\sci_echoback).  Then modify it for SCI-B.  Then integrate both SCI-A and SCI-B.

I lose SCIA RX with this code and No SCIB RX either(SCIATX and SCIB TX still works). Not sure I am importing SCI modules into my project from this demo and that could be causing this.

Thanks and regards,

Vamsi

void InitSysCtrl(void) //Same as CONTROLsuite 

void InitPieCtrl(void)
{
    //--- Disable interrupts
    asm(" SETC INTM, DBGM");
    // Disable global interrupts

    //--- Initialize the PIE_RAM
    PieCtrlRegs.PIECTRL.bit.ENPIE = 0;    // Disable the PIE
    asm(" EALLOW");
    // Enable EALLOW protected register access

    // Step around the first three 32-bit locations (six 16-bit locations).
    // These locations are used by the ROM bootloader during debug, and also
    // by the Flash API algorithms.
    memcpy((Uint16 *) &PieVectTable + 6, (Uint16 *) &PieVectTableInit + 6, 256 - 6);

    asm(" EDIS");
    // Disable EALLOW protected register access

    //--- Disable all PIE interrupts
    PieCtrlRegs.PIEIER1.all = 0x0000;
    PieCtrlRegs.PIEIER2.all = 0x0000;
    PieCtrlRegs.PIEIER3.all = 0x0000;
    PieCtrlRegs.PIEIER4.all = 0x0000;
    PieCtrlRegs.PIEIER5.all = 0x0000;
    PieCtrlRegs.PIEIER6.all = 0x0000;
    PieCtrlRegs.PIEIER7.all = 0x0000;
    PieCtrlRegs.PIEIER8.all = 0x0000;
    PieCtrlRegs.PIEIER9.all = 0x0000;
    PieCtrlRegs.PIEIER10.all = 0x0000;
    PieCtrlRegs.PIEIER11.all = 0x0000;
    PieCtrlRegs.PIEIER12.all = 0x0000;

    //--- Clear any potentially pending PIEIFR flags
    PieCtrlRegs.PIEIFR1.all = 0x0000;
    PieCtrlRegs.PIEIFR2.all = 0x0000;
    PieCtrlRegs.PIEIFR3.all = 0x0000;
    PieCtrlRegs.PIEIFR4.all = 0x0000;
    PieCtrlRegs.PIEIFR5.all = 0x0000;
    PieCtrlRegs.PIEIFR6.all = 0x0000;
    PieCtrlRegs.PIEIFR7.all = 0x0000;
    PieCtrlRegs.PIEIFR8.all = 0x0000;
    PieCtrlRegs.PIEIFR9.all = 0x0000;
    PieCtrlRegs.PIEIFR10.all = 0x0000;
    PieCtrlRegs.PIEIFR11.all = 0x0000;
    PieCtrlRegs.PIEIFR12.all = 0x0000;

    //--- Acknowlege all PIE interrupt groups
    PieCtrlRegs.PIEACK.all = 0xFFFF;

    //--- Enable the PIE
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;		// Enable the PIE

}    // end of InitPieCtrl()


static void sci_a_init(void)
{

    asm(" EALLOW");                             // Enable EALLOW protected register access
    SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1;      // LSPCLK to SCI-A enabled
    asm(" EDIS");                               // Disable EALLOW protected register access

    asm(" EALLOW");                         // Enable EALLOW protected register access
    GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0;     // Enable pull-up for GPIO28 (SCIRXDA)
    GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1;    // 0 = GPIO    1 = SCIRXDA    2 = SDAA       3 = TZ2
    GpioCtrlRegs.GPAPUD.bit.GPIO29 = 1;     // Enable pull-up for GPIO29 (SCITXDA)
    GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1;    // Configure GPIO29 for SCITXDA operation
    asm(" EDIS");                               // Disable EALLOW protected register access

    SciaRegs.SCIFFTX.bit.SCIRST = 1;        // resume transmit or receive
    SciaRegs.SCIFFTX.bit.SCIFFENA = 0;      // use FIFO enhancements
    SciaRegs.SCIFFTX.bit.TXFIFOXRESET = 0;  // re-enable transmit FIFO
    SciaRegs.SCIFFTX.bit.TXFFST = 0;        // empty FIFO
    // SciaRegs.SCIFFTX.bit.TXFFINT = 0;    // read-only 0 = no interrupt, 1 = interrupt has occurred
    SciaRegs.SCIFFTX.bit.TXFFINTCLR = 1;    // clear TXFFINT flag
    SciaRegs.SCIFFTX.bit.TXFFIENA = 0;      // Transmit FIFO interrupt based on TXFFIVL is disabled
    SciaRegs.SCIFFTX.bit.TXFFIL = 0;        // FIFO interrupt level (default to 0)

    // SciaRegs.SCIFFRX.bit.RXFFOVF = 0;    // read-only, 0 = no overflow, 1 = lost characters
    // SciaRegs.SCIFFRX.bit.RXFFOVRCLR = 0;    // Clear FIFO overflow
    SciaRegs.SCIFFRX.bit.RXFFOVRCLR = 0;    // Clear FIFO overflow
    SciaRegs.SCIFFRX.bit.RXFIFORESET = 0;   // Re-enable FIFO
    SciaRegs.SCIFFRX.bit.RXFFST = 0;        // empty
    // SciaRegs.SCIFFRX.bit.RXFFINT = 0;        // read-only 0 = no interrupt, 1 = interrupt has occurred
    SciaRegs.SCIFFRX.bit.RXFFINTCLR = 0;    // clear RXFFINT
    SciaRegs.SCIFFRX.bit.RXFFIENA = 0;      // RX FIFO disabled
    // SciaRegs.SCIFFRX.bit.RXFFIL = 4;         // RX FIFO interrupt level (number of characters in the buffer when interrupt occurs)
    SciaRegs.SCIFFRX.bit.RXFFIL = 0;        // RX FIFO interrupt level

    SciaRegs.SCIFFCT.bit.ABD = 0;           // Autobaud detection not complete
    SciaRegs.SCIFFCT.bit.ABDCLR = 0;        // no effect
    SciaRegs.SCIFFCT.bit.CDC = 0;           // disable autobaud
    SciaRegs.SCIFFCT.bit.FFTXDLY = 0;       // FIFO transfer delay



    SciaRegs.SCICCR.bit.STOPBITS = 0;           // one stop bit
    SciaRegs.SCICCR.bit.PARITY = 0;             // no parity
    SciaRegs.SCICCR.bit.PARITYENA = 0;          // parity disable, none generated
    SciaRegs.SCICCR.bit.LOOPBKENA = 0;          // loopback disabled
    SciaRegs.SCICCR.bit.ADDRIDLE_MODE = 0;      // Idle-line mode protocol
    SciaRegs.SCICCR.bit.SCICHAR = 7;            // 8 bit data

    // SciaRegs.SCICTL1.bit.rsvd1 = 0;
    SciaRegs.SCICTL1.bit.RXERRINTENA = 0;       // disable Rx error
    SciaRegs.SCICTL1.bit.SWRESET = 0;           // initializes SCI and holds in reset
    // SciaRegs.SCICTL1.bit.rsvd2 = 0;
    SciaRegs.SCICTL1.bit.TXWAKE = 0;            // wake-up not used
    SciaRegs.SCICTL1.bit.SLEEP = 0;             // sleep not used
    SciaRegs.SCICTL1.bit.TXENA = 1;             // enable transmitter
    SciaRegs.SCICTL1.bit.RXENA = 1;             // enable receiver

    SciaRegs.SCICTL2.bit.TXINTENA = 1;          // enable Tx complete interrupt
    SciaRegs.SCICTL2.bit.RXBKINTENA = 1;        // enable Rx/Break interrupt
    SciaRegs.SCICTL1.bit.SWRESET = 1;           // release reset

    SCI_SetBaud(PortA, eBaud_9600);
    //  SCI_SetBaudA(eBaud_57600);



    PieCtrlRegs.PIECTRL.bit.ENPIE = 0;      // Disable the PIE, to make changes
    PieCtrlRegs.PIEIER9.bit.INTx1 = 1;      // PIE Group 9, enable INT1 interrupt SCI-A Rx
    //PieCtrlRegs.PIEIER9.bit.INTx2 = 1;   // PIE Group 9, enable INT2 interrupt SCI-A Tx
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;      // Enable the PIE

    IER |= 0x0100;                          // Enable SCIRXINTA in IER to enable PIE group 9
}

static void sci_b_init(void)
{
	// Note: Clocks were turned on to the SCIB peripheral
	asm(" EALLOW");                             // Enable EALLOW protected register access
	SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1;      // LSPCLK to SCI-B enabled
	asm(" EDIS");                               // Disable EALLOW protected register access

    SCI_SelectGaugePort(Port1);

    ScibRegs.SCIFFTX.bit.SCIRST = 1;        // resume transmit or receive
    ScibRegs.SCIFFTX.bit.SCIFFENA = 0;      // use FIFO enhancements
    ScibRegs.SCIFFTX.bit.TXFIFOXRESET = 0;  // re-enable transmit FIFO
    //ScibRegs.SCIFFTX.bit.TXFFST = 0;        // empty FIFO
    // ScibRegs.SCIFFTX.bit.TXFFINT = 0;        // read-only 0 = no interrupt yet, 1 = interrupt has occurred
    ScibRegs.SCIFFTX.bit.TXFFINTCLR = 1;    // clear TXFFINT flag
    ScibRegs.SCIFFTX.bit.TXFFIENA = 0;     // Transmit FIFO interrupt based on TXFFIVL is disabled
    ScibRegs.SCIFFTX.bit.TXFFIL = 0;       // FIFO interrupt level (default to 0)

    // ScibRegs.SCIFFRX.bit.RXFFOVF = 0;    // read-only, 0 = no overflow, 1 = lost characters
    // ScibRegs.SCIFFRX.bit.RXFFOVRCLR = 0;     // Clear FIFO overflow
    ScibRegs.SCIFFRX.bit.RXFFOVRCLR = 0;    // Clear FIFO overflow
    ScibRegs.SCIFFRX.bit.RXFIFORESET = 0;   // Re-enable FIFO
    ScibRegs.SCIFFRX.bit.RXFFST = 0;        // empty
    // ScibRegs.SCIFFRX.bit.RXFFINT = 0;        // read-only 0 = no interrupt, 1 = interrupt has occurred
    ScibRegs.SCIFFRX.bit.RXFFINTCLR = 0;    // clear RXFFINT
    ScibRegs.SCIFFRX.bit.RXFFIENA = 0;      // RX FIFO enabled
    ScibRegs.SCIFFRX.bit.RXFFIL = 0;        // RX FIFO interrupt level

    ScibRegs.SCIFFCT.bit.ABD = 0;           // Autobaud detection not complete
    ScibRegs.SCIFFCT.bit.ABDCLR = 0;        // no effect
    ScibRegs.SCIFFCT.bit.CDC = 0;           // disable autobaud
    ScibRegs.SCIFFCT.bit.FFTXDLY = 0;       // FIFO transfer delay


    ScibRegs.SCICCR.bit.STOPBITS = 0;           // one stop bit
    ScibRegs.SCICCR.bit.PARITY = 0;             // no parity
    ScibRegs.SCICCR.bit.PARITYENA = 0;          // parity disable, none generated
    ScibRegs.SCICCR.bit.LOOPBKENA = 0;          // 0=loopback disabled
    ScibRegs.SCICCR.bit.ADDRIDLE_MODE = 0;      // Idle-line mode protocol
    ScibRegs.SCICCR.bit.SCICHAR = 7;            // 8 bit data
    // ScibRegs.SCICTL1.bit.rsvd1 = 0;
    ScibRegs.SCICTL1.bit.RXERRINTENA = 0;       // disable Rx error
    ScibRegs.SCICTL1.bit.SWRESET = 0;           // initializes SCI and generates a reset
    // ScibRegs.SCICTL1.bit.rsvd2 = 0;
    ScibRegs.SCICTL1.bit.TXWAKE = 0;            // wake-up not used
    ScibRegs.SCICTL1.bit.SLEEP = 0;             // sleep not used
    ScibRegs.SCICTL1.bit.TXENA = 1;             // enable transmitter
    ScibRegs.SCICTL1.bit.RXENA = 1;             // enable receiver

    ScibRegs.SCICTL2.bit.TXINTENA = 0;          // enable Tx complete interrupt
    ScibRegs.SCICTL2.bit.RXBKINTENA = 1;        // enable Rx/Break interrupt
    ScibRegs.SCICTL1.bit.SWRESET = 1;           // reload register after a system reset

    SCI_SetBaud(PortB, eBaud_9600);


    PieCtrlRegs.PIECTRL.bit.ENPIE = 0;      // Disable the PIE, to make changes
    PieCtrlRegs.PIEIER9.bit.INTx3 = 1;      // PIE Group 9, enable INT3 interrupt SCI-B Rx
    //PieCtrlRegs.PIEIER9.bit.INTx4 = 1;      // PIE Group 9, enable INT4 interrupt SCI-B Tx
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;      // Enable the PIE

    IER |= 0x0100;                          // Enable SCIRXINTB in IER to enable PIE group 9

	SCI_B_input_index = 0;
    SCI_B_input[0] = 0;
}


void sci_xmit(SCI_Port p, unsigned char a)
{
    if (p == PortA)
    {
        while (SciaRegs.SCICTL2.bit.TXEMPTY == 0) {}
        SciaRegs.SCITXBUF = (a & 0x00FF);
    }
    else if (p == PortB)
    {
        while (ScibRegs.SCICTL2.bit.TXEMPTY == 0){}
        ScibRegs.SCITXBUF = (a & 0x00FF);
    }
}


void sci_msg(SCI_Port p, unsigned char *msg)
{
    unsigned char *ptr;

    ptr = msg;
    while (*ptr != '\0')
    {
        sci_xmit(p, *ptr);
        ptr++;
    }
}

interrupt void sciaRxFifoIsr(void)
{
    unsigned short data;

    data = SciaRegs.SCIRXBUF.all;   // Read data
    if (bSCI_MessageReceived != TRUE)       // if no pending message waiting
    {
        // check for errors before using data
        if ((SciaRegs.SCIRXST.bit.FE == 0) && (SciaRegs.SCIRXST.bit.OE == 0))
        {
            if ((SCI_NextIndex & 0x01) == 0)
            {
                SCI_RxBuffer[(SCI_NextIndex / 2)].Packed.LSB = (data & 0x00FF);		// Save in LSB
            }
            else
            {
                SCI_RxBuffer[(SCI_NextIndex / 2)].Packed.MSB = (data & 0x00FF);		// Save in MSB
            }
            if (SCI_NextIndex == 0)
            {
                if ((data & 0x00FF) == SyncByte)
                {
                    SCI_NextIndex = 1;
                }
                else
                {
                    // ignore characters until sync found
                }
            }
            else
            {
                // ready to process?

            	   if ((SCI_NextIndex - SCI_StartIndex) >= 4)
            	    {
            	        if (((SCI_StartIndex + SCI_LengthOffset) & 0x01) == 0)
            	        {
            	            if (SCI_NextIndex >= (SCI_RxBuffer[(SCI_StartIndex + SCI_LengthOffset) / 2].Packed.LSB) + 4)
            	            {
            	            	bSCI_MessageReceived = TRUE;
            	            }
            	        }
            	        else
            	        {
            	            if (SCI_NextIndex >= (SCI_RxBuffer[(SCI_StartIndex + SCI_LengthOffset) / 2].Packed.MSB) + 4)
            	            {
            	            	bSCI_MessageReceived = TRUE;
            	            }
            	        }
            	    }


                // point to next empty cell
                if (SCI_NextIndex == ((MaximumMessageSize * 2) - 1))  // last cell
                {
                    SCI_NextIndex = 0U;     // wrap around
                    SCI_Overflow = TRUE;
                }
                else
                {
                    SCI_NextIndex++;        // point to next cell
                }
            }
        }
        else
        {
            // framing error, overrun error, parity not configured and break will be ignored/not used
            // may want to keep track of the number of errors with a counter
        }
    }
    else
    {
        // error, something wrong (pending message not processed in time)
        SCI_Overflow = TRUE;
    }

    SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1;     // Clear Overflow flag
    SciaRegs.SCIFFRX.bit.RXFFINTCLR=1;     // Clear Interrupt flag


    PieCtrlRegs.PIEACK.all |= PIEACK_GROUP9;       // Issue PIE ack (SCI-A)
}

interrupt void scibRxFifoIsr(void)
{
    unsigned short data;

    data = ScibRegs.SCIRXBUF.all;   // Read data
    SCI_B_input[SCI_B_input_index] = data;
    if ((SCI_B_input_index + 1) < SCI_MAX_INPUT)
    {
        SCI_B_input_index++;
    }
    else
    {
        SCI_B_input_index = 0;  // wrap around
        SCI_Overflow = TRUE;    // overflow
    }

    ScibRegs.SCIFFRX.bit.RXFFOVRCLR = 1;   // Clear Overflow flag
    ScibRegs.SCIFFRX.bit.RXFFINTCLR = 1;   // Clear Interrupt flag

    PieCtrlRegs.PIEACK.all |= PIEACK_GROUP9;       // Issue PIE ack (SCI-A)
}
void SCI_SelectGaugePort(GaugePort p)
{
    asm(" EALLOW");                         // Enable EALLOW protected register access

    if (p == Port1)
    {
        // Rx = 23, Tx = 22
        GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0;    // Enable pull-up for GPIO22 (SCITXDB)
        GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3;   // Configure GPIO22 for SCITXDB operation
        GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0;    // Enable pull-up for GPIO23 (SCIRXDB)
        GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3;  // Asynch input GPIO23 (SCIRXDB)
        GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3;   // Configure GPIO23 for SCIRXDB operation
        port = p;       // update current port
    }
    asm(" EDIS");                           // Disable EALLOW protected register access
}

Vamsi,

I have tried both, without success

1. Reduced Baud rate on either ports from 9600 to 1200.

2. Copied the controlSUITE example code for FIFO to either ports.

Still same symptoms - still no SCIB RX (SCIA TX/RX and SCIB TX works).

Pasting FIFO code below

Any further ideas?

Thanks,

Jameel

static void sci_a_init(void)
{

    SciaRegs.SCICCR.all =0x0007;   // 1 stop bit,  No loopback
                                      // No parity,8 char bits,
                                      // async mode, idle-line protocol
   	SciaRegs.SCICTL1.all =0x0003;  // enable TX, RX, internal SCICLK,
                                      // Disable RX ERR, SLEEP, TXWAKE

   	SciaRegs.SCICTL2.bit.TXINTENA =1;
   	SciaRegs.SCICTL2.bit.RXBKINTENA =1;

   	SCI_SetBaud(PortA, eBaud_1200);
    SciaRegs.SCIFFTX.all=0xC022;
    SciaRegs.SCIFFRX.all=0x0022;
    SciaRegs.SCIFFCT.all=0x00;

   	SciaRegs.SCICTL1.all =0x0023;  // Relinquish SCI from Reset
   	SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
    SciaRegs.SCIFFRX.bit.RXFIFORESET=1;
    PieCtrlRegs.PIECTRL.bit.ENPIE = 0;      // Disable the PIE, to make changes
    PieCtrlRegs.PIEIER9.bit.INTx1 = 1;      // PIE Group 9, enable INT1 interrupt SCI-A Rx
    PieCtrlRegs.PIEIER9.bit.INTx2 = 0;   // PIE Group 9, enable INT2 interrupt SCI-A Tx
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;      // Enable the PIE

    IER |= 0x0100;
}

static void sci_b_init(void)
{

    ScibRegs.SCICCR.all =0x0007;   // 1 stop bit,  No loopback
                                      // No parity,8 char bits,
                                      // async mode, idle-line protocol
   	ScibRegs.SCICTL1.all =0x0003;  // enable TX, RX, internal SCICLK,
                                      // Disable RX ERR, SLEEP, TXWAKE

   	ScibRegs.SCICTL2.bit.TXINTENA =1;
   	ScibRegs.SCICTL2.bit.RXBKINTENA =1;

   	SCI_SetBaud(PortB, eBaud_1200);
   	SCI_SelectGaugePort(Port1);

    ScibRegs.SCIFFTX.all=0xC022;
    ScibRegs.SCIFFRX.all=0x0022;
    ScibRegs.SCIFFCT.all=0x00;

   	ScibRegs.SCICTL1.all =0x0023;  // Relinquish SCI from Reset
   	ScibRegs.SCIFFTX.bit.TXFIFOXRESET=1;
    ScibRegs.SCIFFRX.bit.RXFIFORESET=1;
    PieCtrlRegs.PIECTRL.bit.ENPIE = 0;      // Disable the PIE, to make changes
    PieCtrlRegs.PIEIER9.bit.INTx3 = 1;      // PIE Group 9, enable INT3 interrupt SCI-B Rx
    PieCtrlRegs.PIEIER9.bit.INTx4 = 0;      // PIE Group 9, enable INT4 interrupt SCI-B Tx
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;      // Enable the PIE

    IER |= 0x0100;
}

Jameel,

Jameel said:

1. Port A and Port B SCI registers are initialized identically (Please see code)
2. ISR for either ports are identical(as far as Interrupt register usage goes).
3. I can see RX/TX activity on scope on GPIO pins assigned for SCI B, so hardware is functional.

Jameel said:

1. As Interrupt priority of SCI A is higher than port B, could that be an issue?

If you disable SCI-A, does SCI-B work properly?

It is possible that the interrupt rate of one port is too high to service the other port.   Interrupts higher in the PIE table have a higher priority.   Group 1 above Group 2.... and likewise within a group (int 1.1 > int 1.2 > int 1.3.... etc  > int 2.1 > int 2.2 etc...)

Regards

Lori

edit - typo fixed SPI -> SCI