Hi TI Team,
I am going through this blog by TI Dave wilson.
e2e.ti.com/.../the-ten-commandments-of-digital-control-part-5
d. PWM update rate. Most PWM modules have double-buffered PWM value registers, meaning that the PWM values from the software are loaded to an outer set of registers, and then this data is transferred to the active PWM registers at the start of the PWM cycle. However, what many engineers fail to remember is that this adds phase delay to your control system, and must be considered in any stability analysis of your system. While the data is sitting in these outer registers, it is becoming stale. Many PWM modules (such as the ones on our Piccolo family of processors) have the ability to be updated TWICE during each PWM cycle. This not only improves your phase margin a bit, but it allows your system sampling frequency to actually be twice the PWM frequency. This is also a very useful feature with Space Vector Modulated (SVM) systems, since there are two SVM periods for each PWM period.
It use to state that TI piccolo controller have ability to be updated TWICE during each PWM cycle.
So this means that data from the outer PWM buffer can be transferred to the active PWM registers TWICE during each PWM cycle i.e at top & bottom both. have i got this right ?
But If we can change the active PWM rgister values at two places top & bottom, then will it not distort the PWM waveform for that particular time period ?
Because fo first half of time period PWM width will be different from next half of the time period.
But if we go for active PWM registers update at the start of the PWM cycle waveform will not be distorted for both half of the PWM period.
What do you say ?
Regards,
Dinesh
