Hi,
I am using TMS320F28096 with external 20MHz crystal.
In order to have 90MHz for SYSCLK I set up a PLL to *9 /2.
Vcoclk = 20MHz * 9 = 180MHz
SYSCLK = Vcoclk/2 = 90MHz
I found in technical reference that Vcoclk must be at least 50MHz, but what is the maximum limit?
There is no note about that in documentation.
The chip rarely hungs, I want to be sure that PLL is setup correctly, and fequency limit is not exceeded.
Regards,
Piotr
