TMS320F28069: Meaning of CPU data/program read/write and CLA fetch/read/write

Hi Wayne,

Our devices support a harvard achitecture so each core, the c28x and the CLA, have 6 busses connected to all the memories

1.  Program Address Bus (PAB)
2.  Program Data Bus (PDB)
3. Data Read Address Bus (DRAB)
4. Data Read Data Bus (DRDB)
5. Data Write Address Bus (DWAB)
6. Data Write Data Bus (DWDB)

When the cores "fetch" an instruction they do so by first putting the address of the instruction on the PAB and then, reading the instruction on the PDB. Similarly with data reads/writes the core will dump the data location on the D(R/W)AB and then, read from or write to the location using the D(R/W)DB.

From this, you can infer that we are able to fetch code, read and write data in parallel. The arbitration happens when both cores try to access the same RAM, or FLASH block; the access could be a code fetch, data read or write.

Wayne Huang said:

What does that mean by CPU program write?

Now typically the PAB, PDB are used to fetch the code, but you can also use them to write to a location using the PWRITE assembly instruction. I would refer you to the description of the PWRITE instruction in the CPU ISA guide (SPRU430).