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TMS320F28379D: TMS320F28379D Power Sequencing

xiao peng ma
Intellectual 640 points
Part Number: TMS320F28379D

The Power Sequencing Section,

It is noted that "The supplies should ramp to full rail within 10 ms".

Does the "10 ms" mean that the time when the first rail start to ramp to the time when last rail is valid,so the internal POR circuit can work correctly?

  • 0
    TI__Expert 7885 points
    Hello,

    Total ramp time is w.r.t. to each individual supply rail. When ramping VDDIO it must not take longer than 10ms to achieve operating voltage. Same is true for VDD, the total ramp time of VDD must not exceed 10ms.

    Best Regards,
    Adam Dunhoft
  • 0 in reply to Adam Dunhoft
    Intellectual 640 points

    Sorry,I don't understand the meaning of this word "w.r.t:".

    Counld you give me an explanation?

    If 3.3V is powered up first in 10ms and then 1.2V is powered up in next 10ms,

    the POR circuit will work correctly?

  • 0 in reply to xiao peng ma
    TI__Expert 7885 points
    Hello,

    Sorry. w.r.t. = with respect to.

    The 10ms is for each rail itself, not the total time to bring up all rails together.

    Example: You can ramp VDDIO from 0V to 3.3V in 10ms and then ramp VDD from 0V to 1.2V in 10ms for a total of 20ms.

    Two important requirements:
    1. Ramp time for each rail is 10ms or less
    2. Ramp VDDIO before VDD or at the same time (do not ramp VDD prior to VDDIO)

    Best Regards,
    Adam Dunhoft