LAUNCHXL-F28379D Rev1.2: Layout error causing signal contention on ADC channels

Mark Labbato

Other Parts Discussed in Thread: LAUNCHXL-F28379D, TMS320F28379D

Hello E2E community,

TI recently discovered an issue with the LAUNCHXL-F28379D LaunchPad. This issue affects all LaunchPads marked VER: 1.1 and impacts the ability to utilize all of the available ADC channels.

The affected LaunchPads has ADCINA2 shorted to VREFHIB. This error was caused by a via intersecting a trace. It is recommended that users avoid using ADCINA2.

Additionally, manufacturing tolerance variation may cause a short between U1.VIN+ and ADCINB4 or ADCINC4. No issues have been reported on actual hardware, but it is worth noting in case odd behavior is observed.

ADCINA2/VREFHIB contention:

U1.VIN+/ADCINB4/ADCINC4 contention:

These errors will be corrected in a future revision of the LaunchPad. Also, additional modifications to the board design will provide a more flexible evaluation platform for the user. We apologize for any inconvenience this may have caused. Thank you for evaluating our TMS320F28379D MCU!

over 7 years ago

Todd Anderson78572 over 7 years ago

Guru 14640 points

Is there an update to "SPRAAS1C–August 2011–Revised June 2015" that would be useful for this situation?

Mark Labbato over 7 years ago in reply to Todd Anderson78572

Guru 30330 points

Todd,
I am not quite sure I understand what you are asking. I do have a few comments however. First, the document is not applicable to this family of devices. Second, these errors were specific to the layout environment used, not necessarily a design guideline that was not followed.

Todd Anderson78572 over 7 years ago in reply to Mark Labbato

Guru 14640 points

Mark:
You are correct. But, does TI plan to update the document that I mentioned for its newer devices? (Or create a different document?)

permantier over 7 years ago

Intellectual 440 points

Hello Mark,

Is this issue may affect all the adc channels of the launchpad, or just A2, B4, C4 ?

Thank you

Mark Labbato over 7 years ago in reply to Todd Anderson78572

Guru 30330 points

Todd,

I believe that this is on the backlog, but I don't have any firm commitment. Our datasheets are being improved and have some more specific information. Feel free to create a new post with the information that you would like to see in a new hardware design guide, and we will take your feedback into account.

Mark Labbato over 7 years ago in reply to permantier

Guru 30330 points

Permantier,

No, channels other than the one listed are not affected.

For ADCINA2, the signal is intersecting VREFHIB. Typically, you are always going to drive VREFHIB, so you will see the affect on ADCINA2. B4 and C4 may or may not be affected depending on build tolerances of your particular board.

permantier over 7 years ago in reply to Mark Labbato

Intellectual 440 points

Ok, thank you Mark

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LAUNCHXL-F28379D Rev1.2: Layout error causing signal contention on ADC channels