CCS/TMS320F28379D: It looks like CLA doesn't decode assembly opcode [???]

Hi,

Is your code section "Cla1Prog" in a RAMLSx section that is configured for CLA ownership

    MemCfgRegs.LSxMSEL.bit.MSEL_LS? = 1;

    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS? = 1;

If portions of your CLA code are in RAM sections that the CLA does not own you will see weird behavior (overrunning the MSTOP is one such example) when single stepping through CLA code. 

Hi,

For the sake of clarity, I remeber you my code is similar cla_logic_cpu01 present in CONTROL_SUITE.

Anyway, I check my code according to your advice. My TI 2837xD_RAM_CLA_lnk_cpu1.cmd file appears in this way:

#ifdef CLA_C

CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C

MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */

BEGIN : origin = 0x000000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
RAMD0 : origin = 0x00B000, length = 0x000800
RAMD1 : origin = 0x00B800, length = 0x000800
// RAMLS4 : origin = 0x00A000, length = 0x000800
// RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS4_LS5 : origin = 0x00A000, length = 0x001000
RESET : origin = 0x3FFFC0, length = 0x000002

PAGE 1 :

BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */

RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800

RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800

CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}

SECTIONS
{
codestart : > BEGIN, PAGE = 0
.TI.ramfunc : > RAMM0, PAGE = 0 // Section Added at 04/2017
.text : >> RAMD0|RAMD1|RAMLS4_LS5, PAGE = 0
// .text : >> RAMD0|RAMD1|RAMLS4, PAGE = 0
// .text : >> RAMD0|RAMD1|RAMLS5, PAGE = 0
.cinit : > RAMM0, PAGE = 0
.pinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

.stack : > RAMM1, PAGE = 1
.ebss : > RAMLS2, PAGE = 1
.econst : > RAMLS3, PAGE = 1
.esysmem : > RAMLS3, PAGE = 1
Filter_RegsFile : > RAMGS0, PAGE = 1

/* CLA specific sections */
Cla1Prog : > RAMLS4_LS5, PAGE=0
// Cla1Prog : > RAMLS4, PAGE=0
// Cla1Prog : > RAMLS5, PAGE=0

CLADataLS0 : > RAMLS0, PAGE=1
// CLA1DataLS0 : > RAMLS0, PAGE=1
CLADataLS1 : > RAMLS1, PAGE=1
// CLA1DataLS1 : > RAMLS1, PAGE=1
CLA1mathTables : > RAMLS1, PAGE=1 // Section Added at 04/2017

Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1

/* The following section definition are for SDFM examples */
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444

#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} > RAMM0, PAGE = 0
#else
ramfuncs : > RAMM0 PAGE = 0
#endif
#endif

#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS1, PAGE = 1

.scratchpad : > RAMLS1, PAGE = 1
.bss_cla : > RAMLS1, PAGE = 1
.const_cla : > RAMLS1, PAGE = 1
#endif //CLA_C
}

You can see that Cla1Prog is assigned in a joint LS4_LS5 Local Shared RAM. In a section of the main I put the follow code:

...
DINT; // DB - It's present just in InitPieCtrl();

// 7) CLA MEM + TASK Settings
Cla1Regs.MIER.all = 0;
EALLOW;
CpuSysRegs.PCLKCR0.bit.CLA1 = 1;
EDIS;
CLA_configClaMemory();
CLA_initCpu1Cla1();
...

where the function are:

void CLA_configClaMemory(void)
{
extern uint32_t Cla1funcsRunStart, Cla1funcsLoadStart, Cla1funcsLoadSize;
EALLOW;

#ifdef _FLASH
memcpy((uint32_t *)&Cla1funcsRunStart, (uint32_t *)&Cla1funcsLoadStart,
(uint32_t)&Cla1funcsLoadSize);
#endif //_FLASH

// Initialize and wait for CLA1ToCPUMsgRAM [pag. 604 TMR]
MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};

// Initialize and wait for CPUToCLA1MsgRAM
MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};

// MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;
// MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;

MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0;

MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0;

EDIS;
}

void CLA_initCpu1Cla1(void)
{

EALLOW;
Cla1Regs.MVECT1 = (uint16_t)(&Cla1Task1);
Cla1Regs.MVECT2 = (uint16_t)(&Cla1Task2);
Cla1Regs.MVECT3 = (uint16_t)(&Cla1Task3);
Cla1Regs.MVECT4 = (uint16_t)(&Cla1Task4);
Cla1Regs.MVECT5 = (uint16_t)(&Cla1Task5);
Cla1Regs.MVECT6 = (uint16_t)(&Cla1Task6);
Cla1Regs.MVECT7 = (uint16_t)(&Cla1Task7);
Cla1Regs.MVECT8 = (uint16_t)(&Cla1Task8);

Cla1Regs.MCTL.bit.IACKE = 1;
// Cla1Regs.MIER.all = 0x00FF;
Cla1Regs.MIER.all = 0x0001;

// Configure the vectors for the end-of-task interrupt for all
// 8 tasks
PieVectTable.CLA1_1_INT = &cla1Isr1;
PieVectTable.CLA1_2_INT = &cla1Isr2;
PieVectTable.CLA1_3_INT = &cla1Isr3;
PieVectTable.CLA1_4_INT = &cla1Isr4;
PieVectTable.CLA1_5_INT = &cla1Isr5;
PieVectTable.CLA1_6_INT = &cla1Isr6;
PieVectTable.CLA1_7_INT = &cla1Isr7;
PieVectTable.CLA1_8_INT = &cla1Isr8;

// Enable CLA interrupts at the group and subgroup levels
PieCtrlRegs.PIEIER11.all = 0xFFFF;
IER |= (M_INT11 );
EDIS;
}

Also me I had some doubt with a bad MEM's CLA declaration:

MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;

I try to change in:

MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;

but, now, the main code, when reaches the last above istruction, arrive in 0x3FE468 location where no symbols are defined!

I try to separate LS4 and LS5 but happens the same event.

Do you have some advices ? How must I assigned Cla1Prog with correct use of cmd file ?

Thank's for your help.

Hi Vishal,

I try the follow setting and it works well:

1) in cmd file

...
MEMORY
{
PAGE 0 :
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
// RAMLS4_LS5 : origin = 0x00A000, length = 0x001000
...

SECTIONS
{
...
// .text : >> RAMD0|RAMD1|RAMLS4_LS5, PAGE = 0
.text : >> RAMD0|RAMD1|RAMLS4, PAGE = 0
// .text : >> RAMD0|RAMD1|RAMLS5, PAGE = 0
...
Cla1Prog : > RAMLS5, PAGE=0
CLADataLS0 : > RAMLS0, PAGE=1
CLADataLS1 : > RAMLS1, PAGE=1
...

2) in CLA_configClaMemory(void) funtion:
...
// MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;
// MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;
...

So, How Can I assign RAMLS4_LS5 for Cla1Prog? Why doesn't it works in LS4?

Regards

Diego Bellachioma said:

So, How Can I assign RAMLS4_LS5 for Cla1Prog? Why doesn't it works in LS4?

You can assign CLa1Prog to RAMLS4_5, but the portion that allocated LS4 to the CLA is commented out in your code

Diego Bellachioma said:

// MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;
// MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;

Uncomment the two lines pertaining to LS4 and it will work.

Hi,

I ask sorry because I just try this but I added that two post ago and it makes confusion. In the previous I said:

I tried to change cmd file in:

RAMLS4_LS5 : origin = 0x00A000, length = 0x001000
.text : >> RAMD0|RAMD1|RAMLS4_LS5, PAGE = 0
Cla1Prog : > RAMLS4_LS5, PAGE=0

and in main.c (relative functions):

MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;

but, now, the main code, when reaches the last above istruction, goes in 0x3FE468 program location where no symbols are defined!

I try to separate LS4 and LS5 but happens the same event.

If I separate LS4 and LS5 and assigned Cla1Prog : > RAMLS5, PAGE=0 then it works well, otherwise no.

So, what is it the difference between LS4 and LS5 when we use them about CLA ?

Thank's a lot.

Diego Bellachioma said:

RAMLS4_LS5 : origin = 0x00A000, length = 0x001000

When its defined like this you are actually combining physical RAML4 and RAML5 into one logical RAM block and assigning Cla1Prog to it. However, they are still two separate physical blocks and therefore have to both be configured for CLA ownership. In your setup code you need the following lines

// Cla1Prog placed in LS4 and LS5
MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;

Diego Bellachioma said:

.text : >> RAMD0|RAMD1|RAMLS4_LS5, PAGE = 0

Cla1Prog and .text cannot be assigned to the same blocks (RAMLS4_LS5), they cannot share the same space. The RAM ownership is configured for either CLA or C28x. If Cla1Prog is assigned to RAMLS4_LS5 then .text must be assigned to some other RAMs

Hi Vishal,

why TI 2837xD_RAM_CLA_lnk_cpu1.cmd file is configured in this way:
...
/*RAMLS4 : origin = 0x00A000, length = 0x000800*/
/*RAMLS5 : origin = 0x00A800, length = 0x000800*/
RAMLS4_LS5 : origin = 0x00A000, length = 0x001000
...
.text : >> RAMD0|RAMD1|RAMLS4_LS5, PAGE = 0
...
/* CLA specific sections */
Cla1Prog : > RAMLS4_LS5, PAGE=0
...

I tried to put following in my code:

// Cla1Prog placed in LS4 and LS5
MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;

but It doesn't works.

I want summarize my working progress tests. If I use:
...
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
...
.text : >> RAMD0|RAMD1|RAMLS4, PAGE = 0
...
Cla1Prog : > RAMLS5, PAGE=0

and

MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;

so, CLA's code does work. If I use:

...
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
...
.text : >> RAMD0|RAMD1|RAMLS5, PAGE = 0
...
Cla1Prog : > RAMLS4, PAGE=0

and

MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;

again it does work.

Finally, how can I extend memory space code

.text : >> RAMD0|RAMD1| ?, PAGE = 0 [es. RAMGS0, ecc. since is a following memory block. I just tried and it doesn't work ]

and setting a correct Cla1Prog ?

I know that I take advantage from you, but I wish ask you a right linker cmd configuration that extend program space for main code CPU and settings CLA for a good functionally.

Thank's for your helps.

Diego Bellachioma said:

why TI 2837xD_RAM_CLA_lnk_cpu1.cmd file is configured in this way:
...
/*RAMLS4 : origin = 0x00A000, length = 0x000800*/
/*RAMLS5 : origin = 0x00A800, length = 0x000800*/
RAMLS4_LS5 : origin = 0x00A000, length = 0x001000
...
.text : >> RAMD0|RAMD1|RAMLS4_LS5, PAGE = 0
...
/* CLA specific sections */
Cla1Prog : > RAMLS4_LS5, PAGE=0

Yeah that is definitely a bug. Ill file a ticket to fix that, .text should not be assigned to LS4_LS5

Diego Bellachioma said:

text : >> RAMD0|RAMD1| ?, PAGE = 0 [es. RAMGS0, ecc. since is a following memory block. I just tried and it doesn't work ]

You should be able to assign .text to RAMD0, RAMD1 and RAMGS0 (or any GS RAM on page 0) assuming they are on page 0.

.text :>> RAMD0 | RAMD1 | RAMGS0, PAGE = 0

The .text section will be split in 3, .text.1, .text.2 and .text.3

Diego Bellachioma said:

I know that I take advantage from you, but I wish ask you a right linker cmd configuration that extend program space for main code CPU and settings CLA for a good functionally.

You can use this one from C:\ti\c2000\C2000Ware_0_04_00_00\device_support\f2837xd\common\cmd. The CLA program is assigned to RAMLS5, and LS0 and LS1 are CLA data spaces

// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
// Preprocessing -> --define
#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN           	: origin = 0x000000, length = 0x000002
   RAMM0           	: origin = 0x000122, length = 0x0002DE
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMD1            : origin = 0x00B800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMLS5           : origin = 0x00A800, length = 0x000800
   RESET           	: origin = 0x3FFFC0, length = 0x000002

PAGE 1 :

   BOOT_RSVD        : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
   RAMM1            : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */

   RAMLS0          	: origin = 0x008000, length = 0x000800
   RAMLS1          	: origin = 0x008800, length = 0x000800
   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800

   RAMGS0           : origin = 0x00C000, length = 0x001000
   RAMGS1           : origin = 0x00D000, length = 0x001000
   RAMGS2           : origin = 0x00E000, length = 0x001000
   RAMGS3           : origin = 0x00F000, length = 0x001000
   RAMGS4           : origin = 0x010000, length = 0x001000
   RAMGS5           : origin = 0x011000, length = 0x001000
   RAMGS6           : origin = 0x012000, length = 0x001000
   RAMGS7           : origin = 0x013000, length = 0x001000
   RAMGS8           : origin = 0x014000, length = 0x001000
   RAMGS9           : origin = 0x015000, length = 0x001000
   RAMGS10          : origin = 0x016000, length = 0x001000
   RAMGS11          : origin = 0x017000, length = 0x001000
   RAMGS12          : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS13          : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800

   CLA1_MSGRAMLOW   : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH  : origin = 0x001500, length = 0x000080
}

SECTIONS
{
   codestart        : > BEGIN,     PAGE = 0
   ramfuncs         : > RAMM0      PAGE = 0
   .text            : >> RAMD0|RAMD1|RAMLS4,    PAGE = 0
   .cinit           : > RAMM0,     PAGE = 0
   .pinit           : > RAMM0,     PAGE = 0
   .switch          : > RAMM0,     PAGE = 0
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMM1,     PAGE = 1
   .ebss            : > RAMLS2,    PAGE = 1
   .econst          : > RAMLS3,    PAGE = 1
   .esysmem         : > RAMLS3,    PAGE = 1
   Filter_RegsFile  : > RAMGS0,	   PAGE = 1

    /* CLA specific sections */
   Cla1Prog         : > RAMLS5, PAGE=0

   CLADataLS0		: > RAMLS0, PAGE=1
   CLADataLS1		: > RAMLS1, PAGE=1

   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1

   /* The following section definition are for SDFM examples */
   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444

#ifdef __TI_COMPILER_VERSION__
   #if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc : {} > RAMM0,      PAGE = 0
   #endif
#endif

#ifdef CLA_C
   /* CLA C compiler sections */
   //
   // Must be allocated to memory the CLA has write access to
   //
   CLAscratch       :
                     { *.obj(CLAscratch)
                     . += CLA_SCRATCHPAD_SIZE;
                     *.obj(CLAscratch_end) } >  RAMLS1,  PAGE = 1

   .scratchpad      : > RAMLS1,       PAGE = 1
   .bss_cla		    : > RAMLS1,       PAGE = 1
   .const_cla	    : > RAMLS1,       PAGE = 1
#endif //CLA_C
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Thanks Vishal,

With more attention, I just found a solution while I follow your previous advice, before your actual post. I configured cmd file in this way:

...
RAMGS0 -> PAGE =1 in PAGE = 0
...
.text : >> RAMD0|RAMD1|RAMGS0, PAGE = 0
...
Cla1Prog : > RAMLS4_LS5, PAGE=0 how I wanted
...

and then

MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;

in the CPU1 code to assign the right CLA RAM's ownership. Now, at least in RAM, CPU1 and CLA1 code works!

Since, it is my first time that I use this Forum, can you tell me how must conclude this thread ?

Maybe I must press green Verify Answer button ?

Thanks a lot for your patience, advices and helps.

P.S.: I tried to put my code on FLASH and I just got some issue. I believe that the problem is in DELAY_US and some code that must be loaded from FLASH to RAM [es. InitFlash]. Anyway, I want to create a new thread for it.