TMS320F28377D: RAM initialization by the reset causes {WDRS(CPU1) or NMIWDRS(CPU1)}.

Hi,

Q1-1:  I think that, in fact,  the reset causes {WDRS(CPU1) or NMIWDRS(CPU1)} will initialize all the RAM. Is it correct ?

Yes, that is correct.

Q1-2:  Strictly speaking, I think the figure doesn't show the point above, that is, "{WDRS(CPU1) or NMIWDRS(CPU1)} will initialize all the RAM". Is it correct ?

That seems to be correct. I'll discuss this. Table 3-10. Boot ROM Reset Causes and Actions in TRM explains this better.

Q1-3:  Are there any RAM resources which are NOT initialized by the {WDRS(CPU1) or NMIWDRS(CPU1)} ?  My customer is looking for that.

All the RAM locations are initialized. How many locations customers looking for, which are not initialized by WDRS and NMIWDRS ?

Q2: The TRM, spruhm8f, p538, Table 3-15.

Could you please tell me why this address, was reserved for TI-RTOS(Flash) ?  The address is necessary for any reason ? Like an entry point of some callbacks ?

This space is used by TI-ROTS hence reserved (only if using TI-RTOS). If customers are not using TI-RTOS then it is available for customer use.

Regards,

Vivek Singh

Vivek, I appreciate your response.

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Q1-3: 

n> Are there any RAM resources which are NOT initialized by the {WDRS(CPU1) or NMIWDRS(CPU1)} ?  My customer is looking for that.

v> All the RAM locations are initialized. How many locations customers looking for, which are not initialized by WDRS and NMIWDRS ?

n> I will report later. (expecting reserved bits ..) >>>> (Edit:)  2 byte minimum.

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Q2: The TRM, spruhm8f, p538, Table 3-15.

n> Could you please tell me why this address, was reserved for TI-RTOS(Flash) ?  The address is necessary for any reason ? Like an entry point of some callbacks ?

v> This space is used by TI-ROTS hence reserved (only if using TI-RTOS). If customers are not using TI-RTOS then it is available for customer use.

n> Is it just "because reserved" ? It is highly appreciated if you could explain a background why the flash portion of the TI-RTOS is anchored here. We are studying TI-RTOS for this part.

Vivek,

I would update our questions.

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Q1-3:

n> Are there any RAM resources which are NOT initialized by the {WDRS(CPU1) or NMIWDRS(CPU1)} ?  My customer is looking for that.

v> All the RAM locations are initialized. How many locations customers looking for, which are not initialized by WDRS and NMIWDRS ?

n> I will report later. (expecting reserved bits ..) >>>> (Edit:)  2 byte minimum.

n> The latest question is, Are there any RAM or registers which are NOT initialized by the {WDRS(CPU1) or NMIWDRS(CPU1)} ?  Minimum 2 bytes.

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Q1-4:

Could you please advise ?  My customer prefers to double-check your reply [Q1-3] with a formal TI material, like DS, TRM, or wiki.

We found an another thread https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/424691   , then my customer likes to use as much as bits.

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Q2: The TRM, spruhm8f, p538, Table 3-15.

n> Could you please tell me why this address, was reserved for TI-RTOS(Flash) ?  The address is necessary for any reason ? Like an entry point of some callbacks ?

v> This space is used by TI-ROTS hence reserved (only if using TI-RTOS). If customers are not using TI-RTOS then it is available for customer use.

n> Is it just "because reserved" ? It is highly appreciated if you could explain a background why the flash portion of the TI-RTOS is anchored here. We are studying TI-RTOS for this part.