TMS320F28377D: CMPSS Module - Tolerances and Calibration

Answer:

- Let’s assume your trip target is 1.5V. A voltage delta “x” above 1.5v should result in a 1 and that same voltage delta “x” below 1.5V should result in a 0.  Let’s assume your reference for the COMPDAC is 3.0v. To set it to 1.5v which is your trip point, you set DACVAL to 2048, midcode.

Now, there are two errors with this. The COMPDAC has its own offset error and the comparator has its own offset error so in this case, the total offset error you will see is actually the “Static offset error” specified in the DS as +/-25mV. Basically, what this means is, even though ideally a DACVAL of 2048 with 3.0v reference should give you a voltage of 1.5V, because of the COMPDAC offset error and comparator offset error, your negative reference to the CMPSS will be voltage between 1.475V<->1.525V but since you don’t know what that voltage is, you have to calibrate it out and hence your DACVAL might no longer be 2048 but instead somewhere around that. The calibrated DACVAL you get for COMPH will not necessarily be the same trip DACVAL for COMPL and hence you have to calibrate both separately. This is likely what you are seeing.

and yes, you should calibrate out the offset error every time you boot, get the same benefits as run-time calibration of ADC offset error. One way to do that is, let’s assume 1A is your desired trip point. With hysteresis disabled, you sweep the COMPDAC upwards and downwards and average out the two trip points. You set your COMPDAC to this trip value. We don’t provide offset temperature coefficient but if you correctly calibrate your trip point, this shouldn’t be much of an issue.

- We specify the comparator offset as “Input referred offset error” because it doesn’t have an analog output. The offset you will see happens at the input and not the output.

Few other points:

- Every CMPSS module shares some internal components between COMPH and COMPL. If you are using COMPH and COMPL from the same CMPSS module, you have to be mindful of the inter-module trip disturbance magnitude and trip disturbance settling time. Essentially what this means is, a COMPH or COMPL trip will temporarily disturb the other.

This is specified in the DS as “CMPSS DAC output disturbance” and “CMPSS DAC disturbance time” with values 100LSB and 200ns respectively. A trip on COMPL will temporarily disturb the signal on COMPH and vise-versa.

-    Hysteresis is one-way. what does it mean?  the trip 0->1 always happens at the calibrated trip code and not “calibrated trip code + hysteresis_voltage/2”. Hysteresis only happens from 1->0 and not the other way round.