TMS320F28379D: TMS320F28379D, Tech Support

Hi Essam,

You can convert your external signal to differential using a fully differential op-amp like THS4531 or a pair of single-ended op-amps.

You can get an external fast ADC that can do 14-bit or 16-bit single-ended conversions, however it can be challenging to keep the noise low enough to achieve the rated performance (@16-bit resolution with a 3.0V reference, 1 LSB = 45uV) Using differential signaling can make this much easier, since common-mode noise can be cancelled.

Alternately, if you have time in your control loop, you can over-sample using 12-bit mode to get more resolution. For every 4x increase in samples you gain 1 bit of resolution performance. e.g. if you average 4 samples together you should get 1 more bit of ENOB performance, if you average 16 samples you should get 2 bits, ... etc. This gain isn't indefinite; eventually the ADC THD/SFDR will limit the effective performance.

I appreciate your quick response, yes we had before differential input, and we made the DSP to generate a 1.5V reference. However, for some reason our JTAC stop working properly. When we use a single ended conversion our calibration becomes bad but the JTAC works fine. That is at least what my workmate mentioned to me. Thanks.

Hi Essam,

I think if the JTAG is crashing when you use the differential signal conditioning circuits, the most likely cause would be that the signal conditioning circuitry is producing an over/under voltage condition either during normal operation, or during power up.

For example, if your signal conditioning op-amps are powered by +/-5V rails, if you aren't careful you could drive +5V or -5V into the ADC inputs (if you accidentally min or max the op-amp inputs). In this case, the input will start clamping to the 3.3V rail or VSSA. If the clamping current is large enough (>20mA total or >2mA on a single channel) then you could disrupt operation of the device or even permanently damage the device.

This can also happen on power-up/down if the voltage applied to the ADC input is > VDDA. For example even if the signal conditioning op-amp never outputs a voltage greater than 3.3V, if it outputs 3.3V while the VDDA rail is still powered-down the input will clamp to whatever the current value of VDDA is, again potentially disrupting device operation or damaging the device.

Hi Devin,

Thank you very much for this informative and detailed response. I'll let you know what our team think about it.

Regard,

Essam Morad