F28M36P63C2: SysCtlClockGet() returns wrong value if fractional multiplier is used

In the funktion SysCtlClockGet() the "fractional multiplier" is calculated from the calculated "integer multiplier".

The "fractional multiplier" must be calculated from the input value ulClockIn.

Here is the correct code:

unsigned long
SysCtlClockGet(unsigned long ulClockIn)
{
    unsigned long ulClock;

    //If the pll is enabled calculate its effect on the clock
    if((HWREG(SYSCTL_SYSPLLCTL) &
        (SYSCTL_SYSPLLCTL_SPLLEN | SYSCTL_SYSPLLCTL_SPLLCLKEN)) == 3)
    {
        //Calculate integer multiplier
        ulClock = ulClockIn *
                  (HWREG(SYSCTL_SYSPLLMULT) & SYSCTL_SYSPLLMULT_SPLLIMULT_M);

        //Calculate fractional multiplier
        switch((HWREG(SYSCTL_SYSPLLMULT) & SYSCTL_SYSPLLMULT_SPLLFMULT_M) >>
                SYSCTL_SYSPLLMULT_SPLLFMULT_S)
        {
        default:
        case 0:
            break;

        case 1:
            ulClock += ulClockIn / 4;
            break;

        case 2:
            ulClock += ulClockIn / 2;
            break;

        case 3:
            ulClock += (ulClockIn * 3) / 4;
            break;
        }
    }

    //Fixed divide by 2
    ulClock = ulClock / 2;

    //Divide clock by the system clock divider
    switch(HWREG(SYSCTL_SYSDIVSEL) & SYSCTL_SYSDIVSEL_SYSDIVSEL_M)
    {
    default:
    case 0:
        break;

    case 1:
        ulClock /= 2;
        break;

    case 2:
        ulClock /= 4;
        break;

    case 3:
        ulClock /= 8;
        break;
    }

    //Divide clock by the M3 clock divider
    switch(HWREG(SYSCTL_M3SSDIVSEL) & SYSCTL_M3SSDIVSEL_M)
    {
    default:
    case 0:
        break;

    case 1:
        ulClock /= 2;
        break;

    case 2:
        ulClock /= 4;
        break;
    }

    return ulClock;
}