TMS320F28069: 3 phase SPLL implementation

Ravi H

Part Number: TMS320F28069
Other Parts Discussed in Thread: CONTROLSUITE

I'm trying to implement 3 phase SPLL using the solar library provided in controlSUITE.

Using balanced grid e.g.

grid freq = 50; ISR freq = 20k

Please tell me the significance of filter co-efficients A1(not used in the example), B0 and B1. lf, and the filter limit to obtain required output ?

I'm getting f0 approx 50. D component to approx 1 and Q component to approx 0.

The discrete low pass filter equates to:

$y[n] = y[n-1] + k(x[n-1]-y[n-1])$

But in the example provided in controlSUITE

y[n] = y[n-1] + (B0 * x[n]) - (B1 * x[n-1])..........(1)

Please can I know what is the cutoff freq in the above equation?

How does limiting the filter output (200 here) helps ?

Does equation(1) refer to a PI control ? what is the cutoff freq of the output?

In sprabt4a output response calculations are done to obtain the co-eff. Does it filter any freq ? How is the upper limit determined ?

Please help.

over 8 years ago

0 Ravi H over 8 years ago

Expert 1475 points

Any advises ?

0 Chen Jiang ti over 8 years ago in reply to Ravi H

TI__Genius 16065 points

Hi Ravi,

I will give you a reply later today. Thanks.

Best regards,
Chen

0 Chen Jiang ti over 8 years ago in reply to Ravi H

TI__Genius 16065 points

Hi Ravi,

I am not very familiar with SPLL.
Yes, equation(1) refer to digital PI controller. You can refer to the link below for more information on this topic.

www.google.com/url

Best regards,
Chen

0 Ravi H over 8 years ago in reply to Chen Jiang ti

Expert 1475 points

Sir,

I didn't get the effect of changes in B0_lf and B1_lf for SRF PLL, by changing values also proper output was obtained.

Similarly I wanted to know how the values of k1 and k2 of LPF in DD SRF PLL are obtained for a cut-off frequency?

Please guide me.

0 Manish Bhardwaj over 8 years ago in reply to Ravi H

TI__Mastermind 43730 points

Ravi,

1.
Have you looked at
www.ti.com/.../sprabt4a.pdf

and the solar lib documentation?

the B0_lf, B1_lf are used to tune the settling time of the PLL, this is a common structure used in all PLL modules.

I have an excel file located here that walks you through the computation

C:\ti\controlSUITE\libs\app_libs\solar\v1.2

This is a PI structure.

2.
Also please refer to the discussion on k1 and k2 in the research paper P. R. e. al, "Decoupled Double Synchronous Reference Frame PLL for Power Converters Control,"
IEEE Transaction on Power Electronics, vol. 22, no. 2, 2007

it is a low pass filter implementation , no this is not a PI,

we use the hypothesis from the paper to use wf as 30Hz,

with that using the euqations that are in the UG it's simple to get k1 and k2.

Hope this helps.

regards
Manish Bhardwaj

0 Ravi H over 8 years ago in reply to Manish Bhardwaj

Expert 1475 points

Thanks Sir

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TMS320F28069: 3 phase SPLL implementation