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TMS320F28377D: Time delay between IPCSTS and IPCFLG registers.

harish boyina
Intellectual 365 points
Part Number: TMS320F28377D

Hi,

I have set one IPC flag bit[30] from CPU1 using IPCSET register then respected CPU1's IPCFLG[30] and CPU2's IPCSTS[30] were set but I have a query that what is the time delay occurred between these flag modifications.

-I have configured both CPUs at same clock rate.

-If different time clock rates what will be happen(Not done,but small query)

  • 0
    TI__Guru** 115271 points

    Hi 

    IPCFLG and IPCSTS bits will be set with-in couple of cycles after write  (not long delay). If you are looking for exact cycles then I need to check with our design team.

     -If different time clock rates what will be happen(Not done,but small query)

     

    On this device, CPU1 and CPU2 clock frq are always same. 

    Regards,

    Vivek Singh