Hi,
I am using TMS320F28335 as an SPI slave. The master is reading N bytes from the DSP (where N >> 100). The SPI is configured with 16-level FIFO - every time FIFO is not full, an interrupt triggers and fills the FIFO from RAM.
I am trying to achieve minimum total duration of the transmission, therefore trying to increase the SPI clock frequency. However, it seems that when going to higher frequencies, the DSP becomes too slow to refill the FIFO. Although the limit for SPI clock is 12.5 MHz, I am achieving only ~4 MHz at the moment. If I try higher frequencies, I need to add delays between bytes, therefore the total duration does not get shorter.
Q1: does LSPCLK, which clocks the SPI module, affect this process, or not?
Q2: is there any faster way to fill the FIFO from RAM?
Regards,
Dainius
