F28M36P63C2: F28M36P63C2

Hi Thomas,

To support an upper-bound estimation I need the following:

1.) min Vdd

2.) max temp

3.) max altitude

4.) max latitude

5.) max flight time at altitude

Thanks, Rob

Hi Thomas,

A few clarifications.  I am assuming latitude of 45 N since this makes things a bit worse.

Also, I notice you claim 5 minutes at a 50k...can you give me the flight profile.  What I am interested in is

the altitude you spend the most time at - for many avionics it is usually the max altitude but you show flight time

of 5 hrs but only 10 minutes at 50k - what is the max cruising altitude for the 5 hr flight. I do not need much detail

preferably just one altitude, but since the SEU rate is such a strong function of altitude, even the 10 minutes 

at 50k might wash out the other "cruising" altitude if it is significantly lower.

This is probably overkill and it should be considered an upper bound.

assumptions - min voltage, T=85, altitude = 50k ft, Lat = 45N, flight time 5 hours

Since Flash and L1,L2, etc SRAM have ECC they both almost never fail < 0.4 FIT

The SRAM w parity ~ 2625 FIT (of which 90-94% are a single bit and thus detectable)

The random sequential logic ~ 5722 FIT (assuming 10% derating - based on data and literature)

Assuming you did 1M flights of 5 hours each spending 100% of the flight time at 50kfeet,

999,958 flights would have no events

42 flights would have a single event of which about 30% would be detectable (so the system could restart)

0 flights with more than a single upset.

Please let me know if you have any questions.

Rob

assumptions - min voltage, T=85, altitude = 50k ft, Lat = 45N, flight time 5 hours

50,000ft, 5hrs, 45N latitude (I found one typo and redid the model with better info correction)

Flash was < 0.4 and L1,L2, etc SRAM < 0.9 FIT (both have ECC)

The SRAM w parity ~ 202 FIT (of which 90-94% are a single bit and thus detectable) <<<<note I miss typed this and the last re

The random sequential logic ~ 5722 FIT (assuming 10% derating - based on data and literature)

Assuming you did 1M flights of 5 hours each spending 100% of the flight time at 50kfeet,

999,970 flights would have no events

30 flights would have a single event of which about 30% would be detectable (so the system could restart)

0 flights with more than a single upset.

15,000ft, 5hrs, 45N latitude

Flash was < 0.01 and L1,L2, etc SRAM < 0.03 FIT (both have ECC)

The SRAM w parity ~ 6 FIT (of which 90-94% are a single bit and thus detectable) <<<<note I miss typed this and the last re

The random sequential logic ~ 184 FIT (assuming 10% derating - based on data and literature)

Assuming you did 1M flights of 5 hours each spending 100% of the flight time at 15kfeet,

999,999 flights would have no events

1 flights would have a single event of which about 30% would be detectable (so the system could restart)

0 flights with more than a single upset.

Note that both of these are upper-bounds based on 100% memory utilization and 100% sensitivity, assuming that

an error in any bit any time will cause a system error. Also, since I do not have a component count for the sequential 

logic, I used a rough approximation of 15% of the total number of memory bits.  Historically for processors with

fairly large Flash and SRAM bands this is also an over-estimate. The only derating that I applied is on the sequential

logic SEU since it is well documented (both with our own data and in extensive literature on the subject) that upsets

in logic usually only get propagated < 10% on average, I used 10% derating on this.

Hope this is clear and helps with your calculations.

Rob