CCS/TMS320F28379D: ADCRESULTx Register question

Tool/software: Code Composer Studio

Hello every one! 

I have a problem with a multiple SOC and their results.

I need to use 12 channels, for each channel I use singly SOC. I have started with lunching of one channel, have no problem with this, all works perfect.

The next step was to make 4 SOC for 4 channels, and here the problems begins.

By giving 1.5V at channel A0, I've become result in registers ADCRESULT0 and ADCRESULT1 (See Image 1). 

By giving 1.5V at channel A1, in register ADCRESULT1 (all right).

By giving 1.5V at channel A2, I've become no result at all, and so on.

I have read all examples over 10 times, same thing with Technical Manuals... I have no answers found.

What's a reason could be? 

Thank you!

Image 1

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//####################################################################
// ePWM1 100 kHz, 50% Duty cycle;
// ePWM1B=!ePWM1A;
// Deadband = 100ns Rising Edge + 100 nS Falling Edge
// PIN49=ePWM1A PIN51=ePWM1B;
// ADC SOC0, CHSEL0 = Pin09
//####################################################################

// Included Files
//
#include "F28x_Project.h"

//
// Defines
//
#define PRD 499 // Period register 2499=20kHz 499=100kHz 99=500kHz
#define DB 20 // Deadband 1 = 10 nS
#define acqps 14 // Acquisition Window 75ns

//
// Globals
//

//
// Function Prototypes
//
void ConfigureADC(void);
void SetupADCEpwm(void);
__interrupt void adca1_isr(void);

void InitEPwm1Example(void);
__interrupt void epwm1_isr(void);

//
// Main
//
void main(void)
{

InitSysCtrl();

// InitGpio();

CpuSysRegs.PCLKCR2.bit.EPWM1=1;

InitEPwm1Gpio();

//
// Configure the ADC and power it up
//
ConfigureADC();
//
// Setup the ADC for ePWM triggered conversions
//
SetupADCEpwm();

DINT;

InitPieCtrl();

IER = 0x0000;
IFR = 0x0000;

InitPieVectTable();

EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM1_INT = &epwm1_isr;
PieVectTable.ADCA1_INT = &adca1_isr; //function for ADCA interrupt 1
EDIS; // This is needed to disable write to EALLOW protected registers

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;

InitEPwm1Example();

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

IER |= M_INT3;
IER |= M_INT1; //Enable group 1 interrupts
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

PieCtrlRegs.PIEIER3.bit.INTx1 = 1; //PWM
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; //ADC

while(1)
{

} // While end

} // Main end

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

void ConfigureADC(void)
{
EALLOW;

//
//write configurations
//
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

//
//Set pulse positions to late
//
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;

//
//power up the ADC
//
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;

//
//delay for 1ms to allow ADC time to power up
//
DELAY_US(1000);

EDIS;
}

void SetupADCEpwm(void)
{
//
//Select the channels to convert and end of conversion flag
//
EALLOW;

AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert pin A0
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1; //SOC1 will convert pin A1
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2; //SOC2 will convert pin A2
AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3; //SOC3 will convert pin A3

AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps; // 14 = 75ns
AdcaRegs.ADCSOC1CTL.bit.ACQPS = acqps; // 14 = 75ns
AdcaRegs.ADCSOC2CTL.bit.ACQPS = acqps; // 14 = 75ns
AdcaRegs.ADCSOC3CTL.bit.ACQPS = acqps; // 14 = 75ns

AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //trigger on ePWM1 SOCA
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 5; //trigger on ePWM1 SOCA
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 5; //trigger on ePWM1 SOCA
AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = 5; //trigger on ePWM1 SOCA

AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 3; //end of SOC3 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared

EDIS;
}

//
// adca1_isr - Read ADC Buffer in ISR
//
__interrupt void adca1_isr(void)
{

AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

//
// epwm1_isr - EPWM1 ISR
//
__interrupt void epwm1_isr(void)
{
//
// Toggle GPIO31 (LED)
//
// GpioDataRegs.GPATOGGLE.bit.GPIO31 = 1 ;
//
// Clear INT flag for this timer
//
EPwm1Regs.ETCLR.bit.INT = 1;

//
// Acknowledge this interrupt to receive more interrupts from group 3
//
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

//
// InitEPwm1Example - Initialize EPWM1 configuration
//
void InitEPwm1Example()
{
//
// Setup TBCLK
//
EPwm1Regs.TBPRD = PRD; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter

//
// Set Compare values
//
EPwm1Regs.CMPA.bit.CMPA = PRD/2; // Set compare A value
EPwm1Regs.CMPB.bit.CMPB = 0; // Set Compare B value

//
// Setup counter mode
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

//
// Setup shadowing
//
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up
// count
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A,
// down count
EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1B on event B, up
// count
EPwm1Regs.AQCTLB.bit.CAD = AQ_SET; // Clear PWM1B on event B,
// down count

//
// Active Low PWMs - Setup Deadband
//

EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; // ePWMxA - source for Rising-edges, ePWMxB - source for Falling-edges,
EPwm1Regs.DBFED.bit.DBFED = DB;
EPwm1Regs.DBRED.bit.DBRED = DB;

//
// Interrupt where we will change the Compare Values
//
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event

EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC on up-count
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
}

//
// End of file
//