Other Parts Discussed in Thread: TMS320F28335,
I am migrating a design that used two TMS320F28335 devices to a single TMS320F28377D. When I look at the device literature, the ePWM goes from Type 0 (335) to Type 4 (377D), so obviously there are differences, but the 377D has a clock prescalar block in front of the ePWM module that requires me to divide sysclk by 2, if it is greater than 100MHz. Am I correct that this limitation did not exist on the 335 with the Type 0 ePWM, and if so, why was the previous ePWM Type 0 capable of running from a source clock faster than 100MHz but the Type 4 is not? Thanks!
P.S. Question asked and answered here was helpful for confirming that the /2 is required for SYSCLK > 100MHz, but I would still be interested to understand if this limitation is new or always existed and perhaps was missing from earlier device documentation? e2e.ti.com/.../606833
