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TMS320F28335: XCLKIN rise time

Matti Meikalainen
Prodigy 10 points
Part Number: TMS320F28335


I’m currently working with a third party design which has TMS320F28335. I was investigating 30MHz clock signals and found out that rising and falling edges are not as steep as I expected.

Measured 10% to 90% rise time is 7.2ns so the actual rise time is about 6.2ns. That is, the clock signal is out of DSP specification. Now, I have few questions:

Q1:   I didn’t find clear specification how you specify rise time but I assume you mean 10% to 90% rise time. I.e. for 3.0V signal the time is sitting between voltage levels of 0.30V and 2.7V. Is that correct?
Q2:   Is 6.2ns rise time already a problem for DSP performance or do you have some safety margins? How big margins do you have? I mean, what would be an ultimate rise time I should never exceed?

(Green arrow shows the clock signal I'm concerned the most)

  • 0
    Guru 30330 points
    Matti,

    Your pictures did not come thought. Can you try to upload them again?

    1. Generally yes, the rise/fall times should be between 10% and 90% range. At Nominal operating voltage of 3.3 V, you want to see measure the time the signal is between .33 V to 2.97 V. Additionally, The recommended device operating range for VDDIO supply is 3.135 V to 3.465 V. If the device is operating below 3.135 V, we cannot guarantee proper operation of the device.

    2. Again, if the Clock is not below the MAX specification of 6 ns for XCLKIN, we cannot guarantee operation. The MAX is the MAX, and there is no margin above that.

    Thanks,
    Mark