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TMS320F280049: PWM pin output signal is not stable when period and CMPA are fixed

Part Number: TMS320F280049
Other Parts Discussed in Thread: C2000WARE

Hi,

Customer is using F28004x for their digital power application.

Now we have a issue based on our HRPWM demo code (from C2000ware). If we adjust these points, the PWM output duty will be not stable, 10ns difference, that's one PWM clock difference between each duty.

1) Fix the TBPRDHR with a value: (*ePWM[i]).TBPRDHR = 100<8;

2) Fix the TBPRD with a value: 1000;

3) UpDown mode;

4) Shadow load when HR_CTR_ZERO.

5) Fix CMPA with a value: 200;

6) Fix CMPAHR with a value: 100.

In this case, the duty one PWM clock varies. If we change the load mode from HR_CTR_ZERO to HR_CTR_ZERO_PRD, there's no this issue. 

In all of these cases, HRPWM can output successfully. 

We'd like to know, why in HR_CTR_ZERO mode, the duty can't be stable, but with one PWM clock difference between each duty. 

Thanks a lot.

Br, Jordan

  • Is the customer using AUTOCONV or calculating the scale factor periodically?

  • AutoConv is used.
    Scale factor is calculated, or after power up initialize, or periodically. The result is the same.
    Br, Jordan
  • Just to clarify, the PWM duty cycle varies by 10ns from one period to the next? Can you provide oscilloscope images?
  • Yes, I can.
    If you do a test on our EVM, you will find, too.
    Thanks a lot.
    Br, Jordan
  • By evm you mean the F280049 Control Card?

    Can you also tell me which example code you are basing this on?

  • Here's the code:C:\ti\c2000\C2000Ware_1_00_04_00\device_support\f28004x\examples\hrpwm

    Actually there's only one HRPWM demo code.

    Here's the oscilloscope:

    Br, Jordan

  • This is the section which describes what the configuration needs to be. I have highlighted the important part.

    19.2.4.4.1 High-Resolution Period Configuration
    To use High Resolution Period, the ePWMx module must be initialized in the exact order presented.
    The steps below use CMPA with shadow registers and the corresponding HRCNFG bits for hi-resolution
    operation on EPWMxA. For hi-resolution operation on EPWMxB, make the appropriate substitutions with
    the B channel fields.
    1. Enable ePWMx clock
    2. Enable HRPWM clock
    3. Disable TBCLKSYNC
    4. Configure ePWMx registers - AQ, TBPRD, CC, and so on.
    • ePWMx may only be configured for up-count or up-down count modes. High-resolution period is
    not compatible with down-count mode.
    • TBPRD and CC registers must be configured for shadow loads.
    • CMPCTL[LOADAMODE]
    – In up-count mode: CMPCTL[LOADAMODE] = 1 (load on CTR = PRD)
    – In up-down count mode: CMPCTL[LOADAMODE] = 2 (load on CTR=0 or CTR=PRD)
    5. Configure the HRCNFG register such that:
    • HRCNFG[HRLOAD] = 2 (load on either CTR = 0 or CTR = PRD)
    • HRCNFG[AUTOCONV] = 1 (Enable auto-conversion)
    • HRCNFG[EDGMODE] = 3 (MEP control on both edges)
    6. For TBPHS:TBPHSHR synchronization with high-resolution period, set both
    HRPCTL[TBPSHRLOADE] = 1 and TBCTL[PHSEN] = 1. In up-down count mode these bits must be
    set to 1 regardless of the contents of TBPHSHR.
    7. Enable high-resolution period control (HRPCTL[HRPE] = 1)
    8. Enable TBCLKSYNC
    9. TBCTL[SWFSYNC] = 1
    10. HRMSTEP must contain an accurate MEP scale factor (# of MEP steps per EPWMCLK coarse step)
    because auto-conversion is enabled. The MEP scale factor can be acquired via the SFO() function
    described in Section 19.3.
    11. To control high-resolution period, write to the TBPRDHR(M) registers.

    The load needs to occur on both ZRO and PRD. And you double check with this and let me know if this fixes the issue. I believe this is necessary.

  • Hi,
    Yes, you are right.
    If the load mode is HR_CTR_ZERO_PRD, there's no this issue.
    But if the load mode is HR_CTR_ZERO, there's the issue.
    We'd like to know why.
    Thanks a lot.
    Br, Jordan
  • Jordan,

    That's correct - you need to use HR_CTR_ZERO_PRD for this mode.
    The high resolution values are calculated internally and loaded on both Zero and prd match instances.
    For the new values to take effect at both these instances, you need to use this mode.
    Note that these values change internally for correct operation - though there is no change from user.

    -Bharathi.