I need to sample 16 signals 3 of which at approximately 50 kHz (collecting results for 20 ms for signal filtering) the rest at slow rate (1 kHz).
To satisfy this requirement I've thought to use the DMA with ADC running in Continous and cascade sequencer mode.
The ADC can sample every 80ns (as described in the SPRU812A).
By setting the ACQPS to 1111b I can sample all 16 channels at 10 ^ 9 / (80 * 16 * 15) = 52083 Hz, right?
The problem is that DMA can't save all 16 signals for memory space reasons and i prefer not to handle an EOC interrupt every 50kHz, so I've thought to read asynchronously the ADCRESULT of the rest of the signals. Could a race condition occur between the ADC writing and the asynchronous reading of the CPU?
I've read this post http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/688392?TMS320F28035-ADC-result-register-read-write but I did not find information for my DSP in any official document.
