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TMS320F28376S: ADC returns wrong values when CPU rate is changed

Part Number: TMS320F28376S

Hello

The DAC on our firmware are working fine with a CPU clock frequency of 120 MHz. But when I switch the clock to 160 MHz by setting SPLLIMULT from 12 to 16 in the cfg-file and changing CPU_RATE from 8.333L to 6.250L, then the results (the output parameters of readADC, see code below) are for ADCINC2 allways zero instead of the correct value. The results for ADCIND0 and ADCIND1 are zero in about 30% of the time.

I tried to change the acquisition window, which changes the frequency of occurence, but the problem stays.

I also tried to adapt our code more to TI examples (adc_ppb_offset_cpu01.c) by using ADCINTFLG.bit.ADCINT1 instead of ADCCTL1.bit.ADCBSY for polling, then the firmware crashes.

I checked all clock frequencies between 120 and 200 MHz in 10 MHz steps. The errors start at 150 MHz, above 160 MHZ the errors apeear less often.

Best Regards
Jan

Compiler V16.9.5 LTS
SYS/BIOS V6.51.0.15

static void readADC(Uint16& chC2, Uint16& chD0, Uint16& chD1)
{
    EALLOW;
    AdccRegs.ADCSOCFRC1.all = 0x0001;   // Force SOC0 to start conversion
    AdcdRegs.ADCSOCFRC1.all = 0x0003;   // Force SOC0-SOC1 to start conversion
    EDIS;

    DELAY_US(200);

    Uint32 busyWait = 0;
    // Wait until ADC conversions are completed
    while (AdccRegs.ADCCTL1.bit.ADCBSY == 1 || AdcdRegs.ADCCTL1.bit.ADCBSY == 1)
    {
        busyWait++;
        DELAY_US(100);
    }

    chC2 = AdccResultRegs.ADCRESULT0;
    chD0 = AdcdResultRegs.ADCRESULT0;
    chD1 = AdcdResultRegs.ADCRESULT1;

    AdccRegs.ADCINTFLGCLR.all = 0x0003;     // Clear ADCINT1 and ADCINT2 flag
    AdcdRegs.ADCINTFLGCLR.all = 0x0003;     // Clear ADCINT1 and ADCINT2 flag
}

static void configureADC()
{
    EALLOW;
    AdccRegs.ADCCTL2.bit.PRESCALE = 14;         // Inputclock divider = 8 --> 120 MHz / 8 = 15 MHz.
    AdcdRegs.ADCCTL2.bit.PRESCALE = 14;
    CpuSysRegs.PCLKCR13.all = 0x000C;           // enable clock for ADC C and D

    AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
    AdcSetMode(ADC_ADCD, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

    AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;          // Power up ADC C circuitry
    AdcdRegs.ADCCTL1.bit.ADCPWDNZ = 1;          // Power up ADC D circuitry

    DELAY_US(1000);

    // ADCC
    AdccRegs.ADCSOC0CTL.bit.CHSEL = 2;          // ADCINC2
    AdccRegs.ADCSOC0CTL.bit.ACQPS = 43;       // Acquisition window

    // ADCD
    AdcdRegs.ADCSOC0CTL.bit.CHSEL = 0;          // ADCIND0
    AdcdRegs.ADCSOC0CTL.bit.ACQPS = 43;       // Acquisition window

    AdcdRegs.ADCSOC1CTL.bit.CHSEL = 1;          // ADCIND1
    AdcdRegs.ADCSOC1CTL.bit.ACQPS = 43;       // Acquisition window

    EDIS;
}

  • I see you're writing to the ADCCTL2.PRESCALE field before writing to PCLKCR13, but the ADCCTL2 register isn't writable until after you've enabled the ADCs in PCLKCR13. I suspect your ADCCLK is out of the recommended limits detailed in the data sheet. Check your math for the acquisition window as well to make sure it meets the data sheet minimum.

    Whitney