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SM320F28335-EP: ADC Resister INT_ENA_SEQ setting

user5823452
Prodigy 90 points

Part Number: SM320F28335-EP
Other Parts Discussed in Thread: C2000WARE

I would like to know how to use INT_ENA_SEQ of ADC resister.

When I use ADC Module at the following conditions, should INT_ENA_SEQ1 be set to 1? Or, should it be set to 0?

1. Simultaneous Sampling Mode (SMODE_SEL = 1)

2. Cascade Mode (SEQ_CASC = 1)

3. Start/Stop Mode (CONT_RUN = 0)

4. Number of Conversions : 16 (ADCINA0 to 7 and ADCINB0 to 7)

5. Start of Conversion trigger is SOC_SEQ1 set by software writting.

6. I would like to know the end of all 16 conversions by "INT_SEQ1 interrupt flag bit = 1" (or other sign from ADC module).

  • 0
    TI__Genius 14540 points
    Hi,

    The applications engineer supporting this device returns to the office Monday at which time he will respond to your inquiries.

    Thanks.
  • 0 in reply to Christian Yots
    TI__Guru 62930 points
    Sorry for delay.
    Are you aware of the C2000ware examples for the ADC?
    It can be installed from here: www.ti.com/.../c2000ware

    Once installed, you can find examples for the 28335 located in this directory structure.
    C:\TI\c2000\C2000Ware_1_00_05_00\device_support\f2833x\examples

    There are ADC examples for DMA, SEQ_OPVD, SEQMODE, and SOC.

    I believe that INT_ENA_SEQ1 will need to be set and in the SPRU812A, page 20, it indicates that the interrupt flag is set every time SEQ_CNTR reaches 0. It will not restart, since CONT_RUN is 0.

    If this answers your question, please click "Verify it as the answer"
    Regards,
    Wade
  • 0 in reply to Wade Vonbergen
    Prodigy 90 points
    Thank you for your advice.

    For confirmation, I would lilke to ask again.

    When INT_ENA_SEQ1 isn't set to "1", isn't interrupt flag "INT_SEQ1" set to "1" at completion of conversion?

    When I set "INT_ENA_SEQ1 = 0" and "INT_MOD_SEQ1 = 0", interrupt flag "INT_SEQ1" seemed to be set at completion of conversion.

    When software needs to know the completion of conversion by reading "INT_SEQ1" value and doesn't need to be interrupted automatically by INT_SEQ1, does "INT_ENA_SEQ1" need to be set to "1"? Or, doesn't "INT_ENA_SEQ1" need to be set to "1"?
  • 0 in reply to user5823452
    TI__Guru* 83570 points
    The INT_SEQ1 bit is a local bit that indicates the end of the conversion sequence (up to MAX_CONV value). It will get set when the final result from the current conversion is latched into the ADC Result register. This bit is always enabled, so if your SW is polling to determine when the sequence is done there is no setup necessary.
    There is an additional step for future conversions, and that is to write to the INT_SEQ1_CLR bit to clear the INT_SEQ1 bit so it will be ready for the next conversion.

    If the SW is NOT polling the INT_SEQ1 bit then the INT_ENA_SEQ1 bit can be used to pass the INT_SEQ1 bit to the C28x PIE Interrupt controller. This would allow the end of the conversion to trigger the ADCSOC1 ISR vector. Note that in that case the local INT_SEQ1_CLR bit still would need to be used to clear the local bit so that another ISR can be generated. Finally the PIE itself would still need to be configured as well as enable the correct IER and global ISRs.

    Please let me know if this answers your question.

    Best,
    Matthew
  • 0 in reply to MatthewPate
    Prodigy 90 points
    Thank you for your help, Matthew! I understand.
    I will set INT_ENA_SEQ1 to 0 because my SW is polling the INT_SEQ1.