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Original question:

ADS58J63: Differential input impedance of ADC

F28M36P63C2: Serial input impedance of ADC

THOMAS EDWIGES
Prodigy 120 points
Part Number: F28M36P63C2


Hello,

Can somebody tell me the maximum serial impedance to be used with the ADC of the F28M36C63P2 microcontroler.

I have a sallen-key filter then a RC filter at the input of the ADC and I can only find the typical value of ADC input model which is 50ohms.

I use it with a 12-bit conversion and a sampling frequency of 50kHz.

Thank you in advance.

Thomas

  • 0
    TI__Guru 62975 points

    Thomas,

    There is an ADC input model in the TRM that you can reference.

    The sampling capacitor (Ch) needs to settle within your required accuracy range by the end of the programmed ACQPS window.

    -Tommy

  • 0 in reply to tlee
    Prodigy 120 points

    Hello Tommy?

    Thank for your response but I already seen the typical values in the TRM.

    I'm actually in a scenario where I have a RC before the ADC input with a time constant of 100us (needed for antireplying filter) but I want to increase as possible the value of Rs (=50ohms in typical) because my capacitor package doesn’t allow more than 470nF.

    I'm using this configuration for my channel:

    So If i'm right with a sample window of 187ns for a 12bits conversion and a settling accuracy of 0,25 with this expression

     

    I need a charging time constant of Ch of T=187ns/(-ln(0.25/4096) =19.27ns?

    Can you tell me if the capacitor at the input (in my RC circuit) impact this value?

     

    Thank you in advance.

  • 0 in reply to THOMAS EDWIGES
    TI__Guru 62975 points

    Thomas,

    Your source RC filter will absolutely affect the overall settling behavior of the Ch capacitor.

    The equation that you shared is assuming negligible Cp + Csource and where:

    T = Rseries x Ch
    Rseries = Total resistance of Rsource + Ron

    It is useful for approximating the acquisition window for high bandwidth applications with only Rsource to consider.

    For your large RC filter, the system will look more like a 2nd order low-pass passive filter.  The amount of time required for the Ch to settle will be largely dominated by your RC filter.  I assume that you are implementing a low bandwidth application so you will want to make sure that your Csource is large enough to charge Ch by itself.

    I recommend taking a look at this prior discussion: 

    -Tommy

  • 0 in reply to tlee
    Prodigy 120 points

    Hi tommy,

    Thank for the link , it help me a lot.

    Yes in my case i'm am aquiring a signal with a frequency from 360Hz to 800Hz.

    So If I understood from other discussions I have to use at least  Cext=(5pF+1.6pF)*4096*4 = 108.1nF.

    But the Rext doesn't impact the charge or discharge of the Ch so I can stay with the same RC of 100us and take a Rext= 1kOhms.

    Tell me if I am mistaken something.

    Thank you in advance.

    Thomas

    Thomas

  • 0 in reply to THOMAS EDWIGES
    TI__Guru 62975 points
    Thomas,

    Yes, that is correct. In this charge sharing configuration, the contribution of Rext to charging Ch is expected to be very minimal because it is acting as a current choke.

    You may want to play around with a few different ACQPS values once you have the component values finalized. There may be some momentary instability on Ch as the charge is rapidly redistributed between the two capacitors.

    -Tommy
  • 0 in reply to tlee
    TI__Guru 60865 points

    To add a bit:

    In the case of charge sharing, minimal charge is contributed from the source, through Rext, to the ADC input during the S+H.  Because of this, the S+H duration can be minimum/very short regardless of the RC time constant of the external RC (assuming the C is large enough that you are charge sharing).

    However, increasing Rext is not without consequence.  If you imagine Rext becomes infinite what would happen is that each subsequent sample would deplete some charge from Cext, so eventually the voltage on Cext would go to near 0V (assuming the worst case where Ch is 0V at the beginning of every S+H).  When Rext is large, but not infinite, you end up with a sample rate limitation where larger Rext results in more 'droop error' for a given sample rate or where you need to decrease sample rate to maintain the same error level as Rext increases.

    The good news is that this is really easy to simulate in SPICE/TINA.  See the attached TINA file.  You just want to see how far the voltage drops once it reaches equilibrium after many samples.  You'll need to modify the values and times to match your device and conditions.

    ADCChargeShareSampleRate.TSC