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F28M35H52C: PWM 100% duty cycle turns off the output

Robert Tsien
Prodigy 155 points
Part Number: F28M35H52C

I am working with PWM of 2kHz cycle using 16 bit timer set to inverted output. Everything works nicely except at PWM of 100% the output turns off instead of a solid ON. Is there some trick or bug in the silicon?

Works fine up to 99.9% duty cycle.

Frequency is set up as such (during init):

  TimerLoadSet(TIMER0_BASE, TIMER_A, SysCtlClockGet(SYSTEM_CLOCK_SPEED)/2000);   // step 5 - PWM freq 2kHz

PWM is set by calling:

  TimerMatchSet(TIMER0_BASE, TIMER_A, PWM_2K_DUTY_CYCLE(value));

where:

#define PWM_2K_DUTY_CYCLE(x) (uint32_t)((x * M3_PWM_FREQ) / 1000)

#define M3_PWM_FREQ (SysCtlClockGet(SYSTEM_CLOCK_SPEED)/2000)

value is %x10. eg. 999 = 99.9%

  • 0
    TI__Genius 10820 points

    Hi,

    This is expected behavior and described in the section 7.2.4.5 Waveforms for Common Configurations of the technical reference manual

    If you load CMPA/CMPB on zero, then use CMPA/CMPB values greater than or equal to 1. If you load CMPA/CMPB on period, then use CMPA/CMPB values less than or equal to TBPRD-1. This means there will always be a pulse of at least one TBCLK cycle in a PWM period which, when very short, tend to be ignored by the system. If this is not acceptable for your application, please use the method described in  

    I hope this helps.

    Hrishi