TMS320F28069: F28069 WDFLAG seems not set after BOR

Hitoshi,

Thanks for providing the scope shots. After looking at them carefully, I believe you are seeing a POR/BOR release because XRSn in your scope shots transitions back to high a little less than 1ms after the VDDIO voltage starts to go back up.

Need to clarify a few things: A BOR reset is not a watchdog reset. Yes they are both connected to XRSn and they will drive XRSn low when either condition happens. However, they are not the same. I'll try to explain my understanding of things.

A watchdog reset (WDRSTn) happens when the WDCNTR overflows before being cleared. When this overflow happens, WDRSTn will be driven low which will also drive XRSn low for 512 OSCCLK (51.2us). WDFLAG will be set after this. WDFLAG is only set by the rising edge of WDRSTn. In this case, WDRSTn transitions from low to high so will set WDFLAG.

A BOR reset happens when VDDIO voltage falls into the BOR trip range. When this trip happens, XRSn will be forced low. XRSn will return back to high 400-800us later after VDDIO moves out of the BOR trip range. Note that in this case, WDRSTn was never forced low so there was no low to high transition that happened to set WDFLAG.

I believe what your customer is seeing is normal so there is no cause for alarm as far as i'm aware. One important side note: we don't recommend customers use the internal BOR as the main supervisor. It's fine as a backup supervisor. This is because, the BOR trip range is too wide and actually takes the device out of the recommended operating range and reliable device operation is not guaranteed for operation outside the recommended operating range.