Other Parts Discussed in Thread: C2000WARE, TIDM-1001
Dear Champs,
I am asking this for our customer.
On F28004x TRM
http://www.ti.com/lit/ug/sprui33a/sprui33a.pdf
Sec 19.2.4.4.1 (Page 1856)
It says,
When high-resolution period mode is enabled, an EPWMxSYNC pulse will introduce +/- 1 - 2 cycle jitter to the PWM (+/- 1 cycle in up-count mode and +/- 2 cycle in up-down count mode). For this reason, TBCTL[SYNCOSEL] should not be set to 1 (CTR = 0 is EPWMxSYNCO source) or 2 (CTR = CMPB is EPWMxSYNCO source). Otherwise, the jitter will occur on every PWM cycle with the synchronization pulse. When TBCTL[SYNCOSEL] = 0 (EPWMxSYNCI is EPWMxSYNCO source), a software synchronization pulse should be issued only once during high-resolution period initialization. If a software sync pulse is applied while the PWM is running, the jitter will appear on the PWM output at the time of the sync pulse.
In our understanding, EPWMxSYNC will introduce +-1 or 2 cycle jitters when using high-resolution period.
For multi-phase interleaved LLC, say 3-phase interleaved LLC, we are confused how we implement high-resolution period because we have to use EPWMxSYNC to sync between interleaved LLC PWM modules.
Do you have any comment or suggestion for us to sync between 3-phase PWM for LLC DC/DC while avoiding this jitter issue?
Even 1 clock cycle (1/100 MHz = 10 ns) leading to large output ripples is not acceptable in our application.
Wayne Huang
