Tool/software: TI C/C++ Compiler
I want to output CLARAM data to EMIF2 data.
So I wrote CLA C-source code as below.
#define WRITE_SIZE (31)
interrupt void Cla1Task7(void) {
int16 s16_i;
int16 *s_ptr;
volatile int16 *d_ptr;
s_ptr = (int16 *)(&(claram.top));
d_ptr = (volatile int16 *)EMIF2_ADDRESS;
for (s16_i = 0; s16_i < WRITE_SIZE; s16_i++) {
*d_ptr++ = *s_ptr++;
}
}
This code copy only 4 data instead of 31 data i expect.
I change the number of WRITE_SIZE, then I got various result.
WRITE_SIZE=32,29,28 is OK (Full data copied)
WIRTE_SIZE=31(is only 4data),30,33,27(is only 3data) is NG.
I check the assembler code, and find the reason of this error maybe.
[NG case]
In this case, assembler code consists of N times loop every 3 data move.And 3rd data move code and compare for end of loop were mixed as below.
MCMP32 MR2,MR1
MMOVZ16 MR0,*MAR1[#1]++
MMOV16 *MAR0[#1]++,MR0
MMOV16 @__cla_scratchpad_start,MAR0
MNOP
MNOP
MMOVZ16 MR0,@__cla_scratchpad_start
MBCNDD $C$L1,NEQ
The result of MCPM32 is used MBCNDD. But MMOVZ16 after MCPM32 has a posibillity of change a status flag. If CLARAM data is 0, then Z flag is set and MBCNDD make a mistake.
[OK case]
In this case, assembler code consists of N times loop every 2 data move. And 2nd data move code is divided from code end of loop.
MMOVIZ MR2,#0
MMOVZ16 MR0,*MAR1[#1]++
MCMP32 MR2,MR1
MMOV16 *MAR0[#1]++,MR0
MMOV16 @__cla_scratchpad_start,MAR0
MNOP
MNOP
MMOVZ16 MR0,@__cla_scratchpad_start
MBCNDD $C$L1,NEQ
There are no code changing a status flag between MCMP32 and MBCNDD.So this code runs normally.
I used TI compiler v6.2.8 and optimize option is -O3 --opt_for_speed=5.
Is this known bug? Should i use newest compiler?