CCS/LAUNCHXL-F28379D: LAUNCHXL-F28379D SPI CPU2

Hosam

Part Number: LAUNCHXL-F28379D

Tool/software: Code Composer Studio

Hello TI community
I have a F28379D delfino launchpad. I have developed a SPI on CPU1 and it works fine. Now I want to make SPI runs on CPU2. I have assigned the SPI ownership to CPU2 via DevCfgRegs.CPUSEL6 register but it does not work.
here is my steps

-CPU1 code is doing:
1- initialization of SPIA and SPIB Pins
2- assign ownership of SPIA and SPIB to CPU2

and has nothing to execute in its endless loop.

-CPU2 code is doing:
- SPIA and SPIB registers initialization.
- SPIA as a MASTER sends data to SPIB which is the slave.

------------------------------------------Results-------------------------------------

-SPIA sends data well. I tested it using my logic analyzer
-SPIB cant receive data.

any suggestion?.

regards

Hosam

over 5 years ago

0 Veena Kamath over 5 years ago

TI__Mastermind 31525 points

Hi Hosam,

Were you able to write to the SPI B registers from CPU2? Or is the issue only on the receiving part?

Regards,

Veena

0 Hosam over 5 years ago in reply to Veena Kamath

Intellectual 720 points

Hi Veena,
Now, it works fine but SPI with DMA is not working although the same code works on CPU1 at using DMA.

thanks

0 Veena Kamath over 5 years ago in reply to Hosam

TI__Mastermind 31525 points

Hi Hosam,

1. Have you enabled the DMA module on the CPU2 subsystem?
2. Have you provided the SPI ownership to CPU2?
2. If you are using the GSx RAM, have you provided its ownership to CPU2?

Regards,
Veena

0 Hosam over 5 years ago in reply to Veena Kamath

Intellectual 720 points

Hi Veena
1- Yes I do if it was the same on CPU1.
2- Sure, the evidence i can transmit and receive data between SPIA and SPIB on CPU2
3- Yes, i made the ownership. Specifically on the RAMs sections that assigned as a source and destination for DMA registers.

Regards
Hosam

0 Veena Kamath over 5 years ago in reply to Hosam

TI__Mastermind 31525 points

Hi Hosam,

The DMA on CPU2 needs to be enabled separately by CPU2. I hope you are doing that.

Looks like the issue is with the DMA configuration. Were you able to see the DMA registers being updated?

Regards,

Veena

0 Hosam over 5 years ago in reply to Veena Kamath

Intellectual 720 points

Hi Veena,
The issue in DMA in either reading or writing. I can write and read on SPIA and SPIB without DMA correctly.

Regards,
Hosam

0 Hosam over 5 years ago in reply to Veena Kamath

Intellectual 720 points

Hi Veena,
I have discovered that the transmitted array of data are zeroes. when i initialized it to another numbers, no update is happened to this array of data. So I made more global ram to be owned by cpu2. but nothing new.
what do think?

best regards
Hosam

0 Hosam over 5 years ago in reply to Hosam

Intellectual 720 points

Hi Veena,
With respect to data that was not initialized, I have solved it. It was a linker file issue.
But for sorry no transmission is happening via DMA. Sure DMA REGISTERS is updated with my configuration.
Please, let me know your opinion.

regards
Hosam

0 Veena Kamath over 5 years ago in reply to Hosam

TI__Mastermind 31525 points

Hi Hosam,

Could you share the code you are using?

Regards,
Veena

0 Hosam over 5 years ago in reply to Veena Kamath

Intellectual 720 points

Hello Veena,
Thank u for keeping in touch. Here is the codes for both CPU1 & CPU2.

THANKS
Hosam

3060.cpu1.c

// FILE:   Lab1_cpu01.c

#include "F28x_Project.h"     // Device Header File and Examples Include File



void SPIPinsInit(void);
void main(void)
{
// Initialize System Control

    InitSysCtrl();

// Initialize GPIO
    InitGpio();

    DINT;
    InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags
    IER = 0x0000;
    IFR = 0x0000;

// Initialize the PIE vector table
    InitPieVectTable();

// Enable global interrupts and higher priority real-time debug events
    EINT;          // Enable Global interrupt INTM
    ERTM;          // Enable Global realtime interrupt DBGM
    SPIPinsInit();
    EALLOW;
    CpuSysRegs.PCLKCR8.bit.SPI_A = 0;           // Turn off clock on this SPI module
    DevCfgRegs.CPUSEL6.bit.SPI_A = 1;
    CpuSysRegs.PCLKCR8.bit.SPI_B = 0;           // Turn off clock on this SPI module
    DevCfgRegs.CPUSEL6.bit.SPI_B = 1;
    EDIS;
    while( !(MemCfgRegs.GSxMSEL.bit.MSEL_GS0 &
             MemCfgRegs.GSxMSEL.bit.MSEL_GS14&
             MemCfgRegs.GSxMSEL.bit.MSEL_GS15))
    {
        EALLOW;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS0 = 1;

        MemCfgRegs.GSxMSEL.bit.MSEL_GS8 = 1;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS9 = 1;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS10 = 1;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS11 = 1;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS12 = 1;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS13 = 1;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS14 = 1;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS15 = 1;
        EDIS;
    }
// Idle loop
    for(;;)
    {

    }
}
 void SPIPinsInit(void)
 {
    EALLOW;
    // Enable internal pull-up for the selected pins
    GpioCtrlRegs.GPBPUD.bit.GPIO58= 0;                          // Enable pull-up on GPIO58 (SPISIMOA)
    GpioCtrlRegs.GPBPUD.bit.GPIO59= 0;                          // Enable pull-up on GPIO59 (SPISOMIA)
    GpioCtrlRegs.GPBPUD.bit.GPIO60= 0;                          // Enable pull-up on GPIO60 (SPICLKA)
    GpioCtrlRegs.GPBPUD.bit.GPIO61= 0;                          // Enable pull-up on GPIO61 (SPISTEA)

    // Set qualification for selected pins to asynch only
    GpioCtrlRegs.GPBQSEL2.bit.GPIO58= 3;                        // Asynch input GPIO58 (SPISIMOA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO59= 3;                        // Asynch input GPIO59 (SPISOMIA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO60= 3;                        // Asynch input GPIO60 (SPICLKA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO61= 3;                        // Asynch input GPIO61 (SPISTEA)

    GpioCtrlRegs.GPBGMUX2.bit.GPIO58= 3;                        // Configure GPIO58 as SPISIMOA
    GpioCtrlRegs.GPBGMUX2.bit.GPIO59= 3;                        // Configure GPIO59 as SPISOMIA
    GpioCtrlRegs.GPBGMUX2.bit.GPIO60= 3;                        // Configure GPIO60 as SPICLKA
    GpioCtrlRegs.GPBGMUX2.bit.GPIO61= 3;                        // Configure GPIO61 as SPISTEA

    //Configure SPI-A pins using GPIO regs
    GpioCtrlRegs.GPBMUX2.bit.GPIO58= 3;                         // Configure GPIO58 as SPISIMOA
    GpioCtrlRegs.GPBMUX2.bit.GPIO59= 3;                         // Configure GPIO59 as SPISOMIA
    GpioCtrlRegs.GPBMUX2.bit.GPIO60= 3;                         // Configure GPIO60 as SPICLKA
    GpioCtrlRegs.GPBMUX2.bit.GPIO61= 3;                         // Configure GPIO61 as SPISTEA

    // Enable internal pull-up for the selected pins
    GpioCtrlRegs.GPBPUD.bit.GPIO63= 0;                          // Enable pull-up on GPIO63 (SPISIMOA)
    GpioCtrlRegs.GPCPUD.bit.GPIO64= 0;                          // Enable pull-up on GPIO64 (SPISOMIA)
    GpioCtrlRegs.GPCPUD.bit.GPIO65= 0;                          // Enable pull-up on GPIO65 (SPICLKA)
    GpioCtrlRegs.GPCPUD.bit.GPIO66= 0;                          // Enable pull-up on GPIO66 (SPISTEA)

    // Set qualification for selected pins to asynch only
    GpioCtrlRegs.GPBQSEL2.bit.GPIO63= 3;                        // Asynch input GPIO63 (SPISIMOA)
    GpioCtrlRegs.GPCQSEL1.bit.GPIO64= 3;                        // Asynch input GPIO64 (SPISOMIA)
    GpioCtrlRegs.GPCQSEL1.bit.GPIO65= 3;                        // Asynch input GPIO65 (SPICLKA)
    GpioCtrlRegs.GPCQSEL1.bit.GPIO66= 3;                        // Asynch input GPIO66 (SPISTEA)

    GpioCtrlRegs.GPBGMUX2.bit.GPIO63= 3;                        // Configure GPIO63 as SPISIMOA
    GpioCtrlRegs.GPCGMUX1.bit.GPIO64= 3;                        // Configure GPIO64 as SPISOMIA
    GpioCtrlRegs.GPCGMUX1.bit.GPIO65= 3;                        // Configure GPIO65 as SPICLKA
    GpioCtrlRegs.GPCGMUX1.bit.GPIO66= 3;                        // Configure GPIO66 as SPISTEA

    //Configure SPI-A pins using GPIO regs
    GpioCtrlRegs.GPBMUX2.bit.GPIO63= 3;                         // Configure GPIO63 as SPISIMOA
    GpioCtrlRegs.GPCMUX1.bit.GPIO64= 3;                         // Configure GPIO64 as SPISOMIA
    GpioCtrlRegs.GPCMUX1.bit.GPIO65= 3;                         // Configure GPIO65 as SPICLKA
    GpioCtrlRegs.GPCMUX1.bit.GPIO66= 3;                         // Configure GPIO66 as SPISTEA

    EDIS;
 }
// end of file

cpu2.c

//
#include "F28x_Project.h"

//
// Defines
//
#define TXFIFO_LVL          8 // FIFO Interrupt Level
#define TXBURST             (16-TXFIFO_LVL)-1 // burst size should be less than 8
#define TXTRANSFER          (uint32_t)((20/(16-TXFIFO_LVL)) - 1) // [(MEM_BUFFER_SIZE/FIFO_LVL)-1]

#define RXFIFO_LVL          8 // FIFO Interrupt Level
#define RXBURST             RXFIFO_LVL-1 // burst size should be less than 8
#define RXTRANSFER          (uint32_t)((20/RXFIFO_LVL) - 1) // [(MEM_BUFFER_SIZE/FIFO_LVL)-1]

//
// Globals
//
#pragma DATA_SECTION(sdataA, "ramgs0"); // map the TX data to memory
//#pragma DATA_SECTION(rdataA, "ramgs1"); // map the RX data to memory
//#pragma DATA_SECTION(sdataB, "ramgs0"); // map the TX data to memory
#pragma DATA_SECTION(rdataB, "ramgs0"); // map the RX data to memory
Uint16 sdataA[20]; // Send data buffer
Uint16 rdataB[20]; // Receive data buffer


volatile Uint16 *DMADest;
volatile Uint16 *DMASource;

void dma_init(void);
void spi_fifo_init(void);

//
// Main
//
void main(void)
{
    Uint16 i;

    InitSysCtrl();
    //InitSpiaGpio();
    //InitSpibGpio();

    DINT;
    IER = 0x0000;
    IFR = 0x0000;
    InitPieCtrl();
    InitPieVectTable();
    //
    // Step 4. Initialize the Device Peripherals:
    //
    dma_init(); // Set up DMA for SPI configuration

    EALLOW;
    CpuSysRegs.SECMSEL.bit.PF2SEL = 1; // Ensure DMA is connected to Peripheral Frame 2 bridge (EALLOW protected)
    //CpuSysRegs.SECMSEL.bit.PF1SEL = 1; // Ensure DMA is connected to Peripheral Frame 2 bridge (EALLOW protected)

    EDIS;
    spi_fifo_init(); // Initialize the SPI only
    //
    // Initialize the data buffers
    //
    for(i=0; i<20; i++)
    {
        sdataA[i] = i;
        rdataB[i] = 0;
    }

    while(1)
    {
        StartDMACH6();
        StartDMACH5();
    }
}

//
// spi_fifo_init - Initialize SPIA FIFO
//
void spi_fifo_init()
{
    // SPIA FIFO regesters conf
    SpibRegs.SPIFFTX.bit.TXFFIL = TXFIFO_LVL;
    SpibRegs.SPIFFRX.bit.RXFFIL = RXFIFO_LVL; // Set RX FIFO level
    SpiaRegs.SPIFFTX.bit.TXFFIL = TXFIFO_LVL; // Set TX FIFO level
    SpiaRegs.SPIFFRX.bit.RXFFIL = RXFIFO_LVL;
    SpiaRegs.SPIFFTX.bit.SPIFFENA = 1;
    SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1;
    SpiaRegs.SPIFFRX.bit.RXFFINTCLR = 1;
    SpiaRegs.SPIFFRX.bit.RXFFOVFCLR = 1;
    SpiaRegs.SPIFFTX.bit.TXFIFO = 1;
    SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1;
    SpiaRegs.SPIFFTX.bit.SPIRST = 1;
    // SPIB FIFO regesters conf
    SpibRegs.SPIFFTX.bit.SPIFFENA = 1;
    SpibRegs.SPIFFTX.bit.TXFFINTCLR = 1;
    SpibRegs.SPIFFRX.bit.RXFFINTCLR = 1;
    SpibRegs.SPIFFRX.bit.RXFFOVFCLR = 1;
    SpibRegs.SPIFFTX.bit.TXFIFO = 1;
    SpibRegs.SPIFFRX.bit.RXFIFORESET = 1;
    SpibRegs.SPIFFTX.bit.SPIRST = 1;

    //
    // Initialize core SPIA registers
    //
    SpiaRegs.SPICCR.bit.SPISWRESET = 0;
    SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
    SpiaRegs.SPICCR.bit.SPICHAR = (16-1);
 //   SpiaRegs.SPICCR.bit.SPILBK = 1;

    SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
    SpiaRegs.SPICTL.bit.TALK = 1;
    SpiaRegs.SPICTL.bit.CLK_PHASE = 0;
    SpiaRegs.SPICTL.bit.SPIINTENA = 0;
    // Set the baud rate
    SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 0x0f;//SPI_BRR;

    // Set FREE bit
    // Halting on a breakpoint will not halt the SPI
    SpiaRegs.SPIPRI.bit.FREE = 1;

    // Release the SPI from reset
    SpiaRegs.SPICCR.bit.SPISWRESET = 1;

    // Initialize core SPIB registers
    SpibRegs.SPICCR.bit.SPISWRESET = 0;
    SpibRegs.SPICCR.bit.CLKPOLARITY = 0;
    SpibRegs.SPICCR.bit.SPICHAR = (16-1);
  //  SpibRegs.SPICCR.bit.SPILBK = 1;

    SpibRegs.SPICTL.bit.MASTER_SLAVE = 0;
    SpibRegs.SPICTL.bit.TALK = 1;
    SpibRegs.SPICTL.bit.CLK_PHASE = 0;
    SpibRegs.SPICTL.bit.SPIINTENA = 0;

    // Set the baud rate
    SpibRegs.SPIBRR.bit.SPI_BIT_RATE = 0x0f;//SPI_BRR;

    // Set FREE bit
    // Halting on a breakpoint will not halt the SPI
    SpibRegs.SPIPRI.bit.FREE = 1;

    // Release the SPI from reset
    SpibRegs.SPICCR.bit.SPISWRESET = 1;
}

//
// dma_init - DMA setup for both TX and RX channels.
//
void dma_init()
{
    //
    // Initialize DMA
    //
    DMAInitialize();
    //DMASource = (volatile Uint16 *)sdata;
    //DMADest = (volatile Uint16 *)rdata;

    //
    // configure DMACH5 for SPI A TX
    //
    DMACH5AddrConfig(&SpiaRegs.SPITXBUF,sdataA);
    DMACH5BurstConfig(TXBURST,1,0); // Burst size, src step, dest step
    DMACH5TransferConfig(TXTRANSFER,1,0); // transfer size, src step, dest step
    DMACH5ModeConfig(DMA_SPIATX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_ENABLE,
    SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,
    CHINT_END,CHINT_DISABLE);

    //
    // configure DMA CH6 for SPI B RX
    //
    DMACH6AddrConfig(rdataB,&SpibRegs.SPIRXBUF);
    DMACH6BurstConfig(RXBURST,0,1);
    DMACH6TransferConfig(RXTRANSFER,0,1);
    DMACH6ModeConfig(DMA_SPIBRX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_ENABLE,
    SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,
    CHINT_END,CHINT_DISABLE);
}
//
// End of file
//

0 Hosam over 5 years ago in reply to Hosam

Intellectual 720 points

Hello Veena,
Hope u are well. Are my files right?. Let me know your opinion please.

best regards

0 Hosam over 5 years ago in reply to Hosam

Intellectual 720 points

Hello Veena,
Did u see any issue in the attached files.

regards
Hosam

0 Hosam over 4 years ago in reply to Hosam

Intellectual 720 points

Hi Veena

Thanks for your time. U can lock this thread. I have solved my issue.

regards
Hosam

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CCS/LAUNCHXL-F28379D: LAUNCHXL-F28379D SPI CPU2