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CCS/TMS320F28379D: Simultaneous sampling of multiple adcs with the EPWM trigger

Hridya I
Intellectual 400 points
Part Number: TMS320F28379D

Tool/software: Code Composer Studio

Hello,

I am using 28379d for my control. I would like to take in 6 ADC i/p to my controller. Also, I am connecting all 6 to Module A of DSP. ADCINA0,ADCINA1,ADCINA2,ADCINA4,ADCINA5.

I am also using AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5 for EPWM1A triggering SOC0 and same for SOC1,SOC2,SOC3,SOC4, SOC5. Does that mean I will get AdcaResultRegs.ADCRESULT0, AdcaResultRegs.ADCRESULT1, AdcaResultRegs.ADCRESULT2, AdcaResultRegs.ADCRESULT3, AdcaResultRegs.ADCRESULT4,AdcaResultRegs.ADCRESULT5 simultaneously when  EPWM1A zero crossing happens?

 Or is it like, AdcaResultRegs.ADCRESULT0 will be the first one coming since SOC0 has the highest priority and AdcaResultRegs.ADCRESULT5 will be the last as SOC5 has the least priority?

If it is not happening simultaneously as discussed in the later part, what would be the correct way in implementing the same for achieving simultaneous sampling of module A? I donot want to distribute ADC inputs across all modules and would prefer to use just ADC module A.

Thanks

Hridya

  • 0
    TI__Guru 60865 points

    Hi Hridya,

    Refer to the section of the TRM 'Achieving Simultaneous Sampling' (http://www.ti.com/lit/ug/spruhm8h/spruhm8h.pdf).

    Overall, if you want truly simultaneous samples, you will need to use multiple ADC modules in parallel. 

    Otherwise, on a single ADC, conversions will be produced sequentially.  These sequential conversions can be produced in less than 300ns each under optimal conditions.

      

  • 0 in reply to Devin Cottier
    Intellectual 400 points
    Ok thanks for the input. I have implemented ADC module. But i have a different issue now.

    I am calling EPWM1 isr during zero crossing of EPWM1.
    Also,
    EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable EPWM1 SOC on A group
    EPwm1Regs.ETSEL.bit.SOCASEL = 1; // Event when TBCTR = 0
    EPwm1Regs.ETPS.bit.SOCAPRD = 1;


    this is done to do ADC conversion on EPWM1 trigger. How to check whether SOCA is changing it's value on EPWM1 zero crossing?

    I tried doig this to verify that:

    if(EPwm1Regs.ETFLG.bit.SOCA == 1)
    GpioDataRegs.GPADAT.bit.GPIO25 = 1;
    else
    GpioDataRegs.GPADAT.bit.GPIO25 = 0;

    This is not woring. GPIO is always set to 1. I was expecting GPIO toggling once in every PWM period. Should i reset SOC flag once it is generated?

    Please help me to understand.
  • 0 in reply to Hridya I
    TI__Guru 60865 points

    Hi Hridya,

    The most direct way to check the ePWM timings would be to setup the ePWM to directly toggle the ePWM output pin at the same time the SOC is generated.  

    For your GPIO method, you should ensure that the GPIO direction is set to output, and yes, the ETFLG bit needs to be cleared.  You can see the documentation of the flag and clear registers in the TRM (http://www.ti.com/lit/ug/spruhm8h/spruhm8h.pdf) in Table "ETFLG Register Field Descriptions" and  Table "ETCLR Register Field Descriptions".

  • 0 in reply to Devin Cottier
    Intellectual 400 points
    I see that the ADCs of the same module can't be read simultaneously but sequentially. The conversion time per ADC channel in a mdule is close to 10.5 clk cycles. So if I am using all 6 channels of say module A, then ADCINA6 will get convertde only after 63 SYS CLK cycles = 315ns.
  • 0 in reply to Devin Cottier
    Intellectual 400 points
    I have set the GPIO as o/p.
    I am clearing interrupt created by EPWM1 using EPWM1Regs.ETCLR.bit.INT =1 inside my ISR
    You mean to say that I need to clear SOCA from EPWM1 also while executing ISR using EPWM1Regs.ETCLR.bit.SOCA = 1?

    I have read in the manual it is not really needed to clear SOCA flag to recieve the next interrupt unlike INT flag which has to be cleared for getting the next interrupt by CPU.
  • 0 in reply to Hridya I
    TI__Guru 60865 points
    Hi Hridya,

    The ADC conversion time is about 10.5 ADCCLKs, not SYSCLKs (consult the ADC Timings table in the TRM or Datasheet for the exact conversion times) and the total time to sample a conversion is roughly (S+H time) + (conversion time).

    e.g. with S+H time = 100ns, ADCCLK = SYSCLK/4 = 50MHz, and SYSCLK = 200MHz, then 6 conversions will take about 6*(100ns + 10.5*20ns) = 1.8us.

    Yes, the ETFLG will not need to be cleared for the purposes of generating a trigger to the ADC, only if you want to generate an ISR.

    For 'GPIO method' just toggle the GPIO inside the ISR; the GPIO won't exactly correspond to the trigger time (due to ISR context switch latency and delay to execute the code) but the frequency will be correct.

    For the direct toggle method, set ePWMxA pin to toggle at the same time the trigger is generated. e.g. set ePWMxA GPIO mux to selet ePWMxA, if SOCA trigger is generated on CMPA-up count then also use the AQ submodule to toggle ePWMxA on CMPA-up count event. Both the frequency and exact time should correspond to the the ADC triggering time (although note that if the ePWM is not configured correctly, the pin could toggle while the ADC is not triggered or vice-versa).
  • 0 in reply to Devin Cottier
    Intellectual 400 points
    Thanks Devin,

    I did the GPIO toggle method 2 days back and it was working fine when set inside the ISR. That confirmed that the EPWM ISR is getting proerly executed. Also, I checked for the triggering signal AdcaRegs.ADCSOC0CTL.bit.TRIGSEL and it was also toggling at carrier frequency. That confirmed that the ADC SOC is generated once in EPWM period.

    Hridya