Dear Sir ,
1. we are developing board that contain TMS320C28377S and FPGA, the interface between them is via EMIF1 16 bit asynchronous.
2.we are able to read / write from to FPGA (there is actually memory implemented in the FPGA)
3.we are seeing some behavior that we don't fully understand, when we make continues write or read (e.g reading few words or writing to few words) , we are seeing
that CS signal asserting and deasserting for every word (16bit) , while we expected to see the CS signal asserted for at least few words, we have try is using DMA and CPU.
while reading application note Design and Usage Guidelines for the C2000™ External Memory Interface (EMIF) its written in chapter 1.2
" The EMIF will hold CS asserted between pipelined operations ... "
Is this expected behavior ?
