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Part Number: TMS320F28035
A. Many C2000 devices have internal circuitry to detect if a watchdog reset (WDRST) or a Power-on-Reset (POR)/External reset (by way of activating the -XRS pin) has occurred. This article describes how this circuitry works and the system requirements on –XRS pin if the WDFLAG is to be used in a system. This article is applicable to 2823x/2833x/2802x/2803x/2805x/2806x devices. For any possible differences in the way this mechanism works across different part numbers, refer to the datasheet & Technical Reference Manual (TRM) of the respective devices.
Calculations on this page assume OSCCLK ≈ 9 MHz.
The WDFLAG bit in the Watchdog module is meant to allow a system to distinguish between a watchdog reset (WDRST) or a Power-on-Reset (POR)/External reset. There is circuitry within the device that samples the -XRS line, after a delay, to distinguish between a watchdog reset (WDRST) and a POR/External reset.
When the -XRS line is pulled low, the WDFLAG bit is forced low. The WDFLAG bit will only be set if the -XRS pin is sampled high after a delay of 8192 * 4 + 512 OSCLK cycles. If the -XRS pin is sampled low at this time, the WDFLAG bit will remain at 0. Therefore to distinguish between a watchdog reset and an external device reset, an external reset must be longer in duration than this sampling time.
Note: OSCCLK is four times SYSCLKOUT at reset. 8192 SYSCLKOUT cycles translates to 8192 * 4 OSCCCLK cycles. This is where the multiply-by-4 comes from in the delay formula, since the delay is expressed in terms of OSCCLK. WDRST is 512 OSCCLKS so the delay is added on to this value.
The following summarizes how the WDFLAG bit behaves for each type of reset:
POR or External-reset after power-up
In this case, the desire is for the WDFLAG bit to be “0” to indicate the reset was not caused by a WDRST. To achieve this, XRS must be held low for longer than (8192 * 4 + 512) OSCCLK cycles. At this point, the -XRS line will be sampled and if it is low, the WDFLAG will remain at 0. For devices with INTOSC = 10 MHz, the time is ~3.7ms for a 9 MHz OSCCLK.
Note: A lower-bound value of 9 MHz, instead of 10 MHz, has been used for the OSCCLK frequency. This is to account for oscillator frequency deviation before calibration.
If the -XRS pin is not low at the sampling time, the WDFLAG bit will be set, incorrectly indicating that the watchdog fired the reset.
On a Watchdog initiated reset (WDRST)
In this case we want the WDFLAG bit to be “1”. Upon a WD counter overflow, the internal WD reset signal (WDRST) will pull the -XRS line low for (just) 512 OSCCLK cycles. When WDRST releases the line, the –XRS pin will return to a high state after a time determined by the capacitance seen by the –XRS pin. The design must ensure that –XRS pin becomes high before 8192 * 4 + 512 OSCLK cycles, which is when the –XRS pin will be sampled. If it is sampled high, WDFLAG will be set. Note that the WDFLAG is set only after (8192 * 4) OSCLK cycles from the time when the WDRST is de-asserted (goes high). Since WDRST is 512 OSCLK cycles wide, WDFLAG flag will be set ~3.7 mS after the start of WDRST (when it goes low).
Connections for –XRS pin
Depending on application needs, the XRS pin may have to be treated differently across designs.
Case 1: Differentiation between WDRST and POR/External reset is not required:
If differentiating between a watchdog reset and a POR/external reset is not a concern, then a pull-up resistor on the -XRS pin (for noise immunity reasons) would suffice. Some controlCARDs have a simple pull-up and falls into this case. The below figure shows why using a simple RC circuit can result in the WDFLAG being incorrectly set if OSCCLK ≈ 9 MHz.
Case 2: Differentiation between WDRST and POR/External reset is required:
If differentiating between a Watchdog Reset and a POR/external reset is needed, additional design considerations are warranted.
There is a circuit in the device that delays the sampling of the XRS line to distinguish between a watchdog reset (WDRST) and a normal reset. To distinguish between a watchdog reset and an external device reset, the external reset must be longer in duration than the watchdog pulse (512 OSCCLK cycles) + a 8192 SYSCLKOUT cycle delay.
On reset, SYSCLKOUT = OSCCLK/4. Therefore, the external reset pulse needs to be longer than 3.7 ms.
Using a supervisor IC
An open-drain supervisor IC may be used as a robust solution which also will protect against power supply brown out conditions.
POR Case: The delay of reset de-assertion by the supervisor should be sufficiently long to hold -XRS low longer than 3.7ms.
WDRESET Case: The use of an open-drain circuit will allow the -XRS output to drive low for 512 OSCCLK cycles and recover to a high level before the sampling of -XRS at 3.7ms to set WDFLAG.
Using a Capacitor and Resistor Circuit
The diode is used to discharge the XRS pin on power-down. In this case, current calculations on the diode should be done assuming the cap is fully charged at 3.3V. If the diode cannot handle the discharge current, then a current limiting resistor in series with the diode may be needed.
Using a buffered R-C Circuit
Hareesh Janakiraman, C2000 Microcontroller Applications, Texas Instruments.
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