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TMS320F28377D: SPI Receive Data Error

Genius 3095 points
Part Number: TMS320F28377D

Dear team:

I simulated 28377D MCBSP as SPI to communicate with CPLD, set up DSP as host and CPLD as slave (only one slave).

I checked that the chip selection, CLK and transmission signal are normal, and the data sent by CPLD to the DSP can also be seen through the oscilloscope. But in the CCS on-line simulation, we observed that DRR1 always displayed 0xFF. What could cause this?

Best regards

  • Is it just the CCS Registers window that displays the incorrect value or does reading DRR1 into a variable also put an incorrect value in the variable? Can you confirm that your pin muxing for the DR pin is correct?

    Whitney

  • Dear Whitney:

    I'm transferring MCBSP to SPI port. In order to verify whether it is a hardware problem, I configure these four pins into SPI first, and observe the data sent and received by CPLD communication. When configuring SPI, there is no problem with the data sent and received. But if these four ports are configured as SPI ports of MCBSP extension, the data received will be problematic. McbspbReg.DRR1.all = 0xFF, and always 0xFF(I sent with 16 bits).

    It seems that the input bus has been pulled up all the time. But the level of GPIO ports entering the DSP is correct, not all of them are high. I don't know where the configuration went wrong. Here's my initialization configuration:

    McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate// generator & transmitter
    McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word

    McbspaRegs.PCR.bit.all = 0x0F08; 
    McbspaRegs.SPCR1.bit.DLB = 0; 

    McbspaRegs.SPCR1.bit.CLKSTP = 3; 
    McbspaRegs.PCR.bit.CLKXP = 0;
    McbspaRegs.PCR.bit.CLKRP = 1;

    McbspaRegs.RCR2.bit.RDATDLY = 01; // RX data delay is 1 bit
    McbspaRegs.XCR2.bit.XDATDLY = 01; // TX data delay is 1 bit

    McbspaRegs.RCR1.bit.RWDLEN1 = 2; // 16-BIts word
    McbspaRegs.XCR1.bit.xWDLEN1 = 01; // 16-BIts word

    McbspaRegs.SRGR2.bit.all = 0x2000; 
    McbspaRegs.SRGR1.bit.all = 19; 

    McbspaRegs.SPCR2.GRST=1; 
    delay_loop();
    McbspaRegs.SPCR2.XRST=1; 
    McbspaRegs.SPCR1.RRST=1; 
    McbspaRegs.SPCR2.FRST=1;

    Best regards

  • Dear Whitney:

    Wait for your reply.

    Thank you.

  • Can you look at the table in the device's technical reference manual that describes the bit settings required to run in clock stop mode? It's called "Table 21-14. Bits Used to Enable and Configure the Clock Stop Mode" in rev H of the document. Make sure your settings match exactly. It can see most of it in the code you shared, but please check the other fields mentioned in the document.

    Thanks,

    Whitney